From nobody Sat Feb 22 08:40:40 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8191C1EE03C for ; Tue, 7 Jan 2025 11:34:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736249704; cv=none; b=dbBWlFXmQ/Eaw7ZBSWWbK/J9ZvZRpj0xxyoYFhx7ahK5DNhJC6amStm+kLvYoGEiCSRl/1en+WwbR9/X/xkkDoXjM9BzrtIcY6Wzua72HAREClsN8hIAujcVl7haYJdmTit/bwaEwHtkPZcBxo9JoJg7W/28dK8Cp7ksHa6rEsI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736249704; c=relaxed/simple; bh=drMaQb3MdyN7tqXWFwHoVuRjxKHh4z/QTt8Iidr2SCQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gTb0f/hcZkXQzBxEzfdjo+MuIyrBPbvb3dEhv5ZCLavvmqXf8X6FXw2ks3CR6xUTSxPEgLhM2Ol32uDfr7l1hhpS/qBO/X8Lp1hu58jGB+CLzRd3C9ZWrLeEgQq/aVmdMX4nzDSnU0sZ4grg7kWHAx176aPcFf888NGAcd2Ur8M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Ha6FrNJb; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Ha6FrNJb" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-43618283d48so111400985e9.1 for ; Tue, 07 Jan 2025 03:34:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736249698; x=1736854498; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BppzZqICDIuXzcoVaHw/k3QGylTLzE7ExLc+N8DKJB4=; b=Ha6FrNJbDFMxY0tg054GiX/lFC0gQ46HbwoQgmuzsgfH8HdcEJKS1bKLoc0QIYC5qW cV6D3JQm3QPweesEzAXSu4DHMUwPdWW8MnBmIOrDSTCvWQIsgXU9pcV+5Efc9lEkeKMl pHAAXt45NysmG0YChPQPXhh0lwiaCWtXpxYZ4UfIFfmGdzKBA/A9H0I9Db1XbtMhoNhc haIwSmFi9/XE56JJOPN/aB6YfDYa6RKH/rnNwQKITC+Mt/S5bJXaxg8QRDKOFV9l3C5I qMxCaxJGJjX25Bl5MVy29bNwMc/Bmxvvem+RJWedU8a8mhJtM/tFel9tRBU0aAhSB9CH VZAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736249698; x=1736854498; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BppzZqICDIuXzcoVaHw/k3QGylTLzE7ExLc+N8DKJB4=; b=MBLgCfDwg4U9xmb+QYSg6UWiRH2yjIEiXF6dNm2kYiHVwxGftRnFUetig6TQl8B6pD BMG8ESqavjMSMcdxuDkYrK5XsRyYTdkScZzNGCz18LSmJqQOcpxP5+fayGYBojx/WW9G VZ7KlEUp34ThydOyoeQPZEKDXMz3qyPNmOncigm3voQh3RqIOY8qJNr3aPzSR1HV9p0A DXqhcIh94KDgmuuxJJ+7yTA1q+mAIjZh1mdMdhl7DGqf9P0J4rrOLHbUhDhSDjx2HLFq gYtcbgMMYJdIQb0MUhiO39VSkA8hZVrN5iybfki7Z+b3xhPXIh8emoRSKvD17hlbpvvu H6pg== X-Forwarded-Encrypted: i=1; AJvYcCVNWcqScNpVC+9paUOe79QvmNWXaVo3XdVf55EYu7oqcRHrykleN7IHlUiOb7Ldag45skMnGr8UPkQUC4k=@vger.kernel.org X-Gm-Message-State: AOJu0Yx91DYbcDrjG+X4cFCZj2JouyFFZHrH7IlkqX8uqznlqctReocO TRD907V2tc34hNv1P68mY7w7HHrbJonxlPLw3vshB234HGnLXckUqHxc3+PYcNM= X-Gm-Gg: ASbGncvZw8HhtNbUjIvMUY+/q5uGqWQEc//UaiUJlIgM35EEJXacdXcUwnO+NWxVtLm jaKFW2TFaCCzym9Q0tVeiFit/nkcISzmdJ/NKx3S2CFgmrXxgE4c5KUAEWZ7aFttsd0F7xkaRK1 uBbj2KPrft02Z7GoJtrqIVkJTwPgWdx2khdq0WOJJcz/KQPKsLDLUMhWMvpH91WD4ckZUq1zGjb Nk2A8WMbjYqR78zBRkVIRNtuN7wBwKaiXMONMm/YjdBhpdrGOspTD6P X-Google-Smtp-Source: AGHT+IHbbqMsVouH91OdV8KnMQ8MWBA16k416qmoq9omp3TMxv8sl0fEiUNFYol+SJHdemxMmyVdqA== X-Received: by 2002:a5d:47c9:0:b0:38a:615c:8223 with SMTP id ffacd0b85a97d-38a615c82bemr20141492f8f.10.1736249697667; Tue, 07 Jan 2025 03:34:57 -0800 (PST) Received: from pop-os.. ([145.224.66.180]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c89e1acsm50299218f8f.68.2025.01.07.03.34.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2025 03:34:57 -0800 (PST) From: James Clark To: maz@kernel.org, kvmarm@lists.linux.dev, oliver.upton@linux.dev, suzuki.poulose@arm.com, coresight@lists.linaro.org Cc: James Clark , Mark Brown , James Clark , Joey Gouly , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Alexander Shishkin , Mark Rutland , Shiqi Liu , James Morse , Anshuman Khandual , Fuad Tabba , "Rob Herring (Arm)" , Raghavendra Rao Ananta , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 06/10] arm64/sysreg/tools: Move TRFCR definitions to sysreg Date: Tue, 7 Jan 2025 11:32:43 +0000 Message-Id: <20250107113252.260631-7-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250107113252.260631-1-james.clark@linaro.org> References: <20250107113252.260631-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Clark Convert TRFCR to automatic generation. Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous definition so no code change is required. Also add TRFCR_EL12 which will start to be used in a later commit. Unfortunately, to avoid breaking the Perf build with duplicate definition errors, the tools copy of the sysreg.h header needs to be updated at the same time rather than the usual second commit. This is because the generated version of sysreg (arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared and tools/ does not have its own copy. Reviewed-by: Mark Brown Signed-off-by: James Clark Signed-off-by: James Clark Reviewed-by: James Clark --- arch/arm64/include/asm/sysreg.h | 12 --------- arch/arm64/tools/sysreg | 36 +++++++++++++++++++++++++++ tools/arch/arm64/include/asm/sysreg.h | 12 --------- 3 files changed, 36 insertions(+), 24 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index b8303a83c0bf..808f65818b91 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -283,8 +283,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) =20 -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) =20 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -519,7 +517,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) =20 -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) @@ -983,15 +980,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) =20 -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4ba167089e2a..ef8a06e180b3 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1997,6 +1997,22 @@ Sysreg CPACR_EL1 3 0 1 0 2 Fields CPACR_ELx EndSysreg =20 +SysregFields TRFCR_ELx +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4:2 +Field 1 ExTRE +Field 0 E0TRE +EndSysregFields + +Sysreg TRFCR_EL1 3 0 1 2 1 +Fields TRFCR_ELx +EndSysreg + Sysreg SMPRI_EL1 3 0 1 2 4 Res0 63:4 Field 3:0 PRIORITY @@ -2546,6 +2562,22 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg =20 +Sysreg TRFCR_EL2 3 4 1 2 1 +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0000 USE_TRFCR_EL1_TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4 +Field 3 CX +Res0 2 +Field 1 E2TRE +Field 0 E0HTRE +EndSysreg + + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 @@ -2956,6 +2988,10 @@ Sysreg ZCR_EL12 3 5 1 2 0 Fields ZCR_ELx EndSysreg =20 +Sysreg TRFCR_EL12 3 5 1 2 1 +Fields TRFCR_ELx +EndSysreg + Sysreg SMCR_EL12 3 5 1 2 6 Fields SMCR_ELx EndSysreg diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/inclu= de/asm/sysreg.h index 345e81e0d2b3..150416682e2c 100644 --- a/tools/arch/arm64/include/asm/sysreg.h +++ b/tools/arch/arm64/include/asm/sysreg.h @@ -283,8 +283,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) =20 -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) =20 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -519,7 +517,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) =20 -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) @@ -983,15 +980,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) =20 -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0) --=20 2.34.1