Documentation/arch/arm64/booting.rst | 18 +++++ arch/arm64/include/asm/el2_setup.h | 25 +++++++ arch/arm64/tools/sysreg | 103 +++++++++++++++++++++++++++ 3 files changed, 146 insertions(+)
This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already being used in the kernel. This is required to prevent their EL1 access trap into EL2. PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged for now as it does not get accessed in the kernel, and there is no plan for its access from user space. I have taken the liberty to pick up all the review tags for patches related to tools sysreg update from the KVM FGT2 V2 patch series posted earlier. https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/ Rob had earler mentioned about FEAT_FGT2 based trap control requirement for FEAT_PMUv3p9 registers that are currently being used in kernel. The context can be found here. https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/ This series is based on v6.13-rc3 Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Ryan Roberts <ryan.roberts@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mark Brown <robh@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: Oliver Upton <oliver.upton@linux.dev> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Eric Auger <eric.auger@redhat.com> Cc: kvmarm@lists.linux.dev Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Anshuman Khandual (7): arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 arm64/sysreg: Add register fields for HDFGRTR2_EL2 arm64/sysreg: Add register fields for HDFGWTR2_EL2 arm64/sysreg: Add register fields for HFGITR2_EL2 arm64/sysreg: Add register fields for HFGRTR2_EL2 arm64/sysreg: Add register fields for HFGWTR2_EL2 arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 Documentation/arch/arm64/booting.rst | 18 +++++ arch/arm64/include/asm/el2_setup.h | 25 +++++++ arch/arm64/tools/sysreg | 103 +++++++++++++++++++++++++++ 3 files changed, 146 insertions(+) -- 2.25.1
On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote: > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already > being used in the kernel. This is required to prevent their EL1 access trap > into EL2. > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged > for now as it does not get accessed in the kernel, and there is no plan for > its access from user space. > > I have taken the liberty to pick up all the review tags for patches related > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier. > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/ > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for > FEAT_PMUv3p9 registers that are currently being used in kernel. The context > can be found here. > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/ > > This series is based on v6.13-rc3 > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: Ryan Roberts <ryan.roberts@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Mark Brown <robh@kernel.org> > Cc: Rob Herring <robh@kernel.org> > Cc: Oliver Upton <oliver.upton@linux.dev> > Cc: Jonathan Corbet <corbet@lwn.net> > Cc: Eric Auger <eric.auger@redhat.com> > Cc: kvmarm@lists.linux.dev > Cc: linux-doc@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > > Anshuman Khandual (7): > arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 > arm64/sysreg: Add register fields for HDFGRTR2_EL2 > arm64/sysreg: Add register fields for HDFGWTR2_EL2 > arm64/sysreg: Add register fields for HFGITR2_EL2 > arm64/sysreg: Add register fields for HFGRTR2_EL2 > arm64/sysreg: Add register fields for HFGWTR2_EL2 > arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 In case it is not clear, this series should be applied to 6.13 as the 2 PMUv3p9 features already landed in 6.13 (per counter EL0 control) and 6.12 (ICNTR). Rob
On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > being used in the kernel. This is required to prevent their EL1 access trap
> > into EL2.
> >
> > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > for now as it does not get accessed in the kernel, and there is no plan for
> > its access from user space.
> >
> > I have taken the liberty to pick up all the review tags for patches related
> > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> >
> > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> >
> > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > can be found here.
> >
> > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> >
> > This series is based on v6.13-rc3
> >
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: Marc Zyngier <maz@kernel.org>
> > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Mark Brown <robh@kernel.org>
> > Cc: Rob Herring <robh@kernel.org>
> > Cc: Oliver Upton <oliver.upton@linux.dev>
> > Cc: Jonathan Corbet <corbet@lwn.net>
> > Cc: Eric Auger <eric.auger@redhat.com>
> > Cc: kvmarm@lists.linux.dev
> > Cc: linux-doc@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > Cc: linux-arm-kernel@lists.infradead.org
> >
> > Anshuman Khandual (7):
> > arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> > arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > arm64/sysreg: Add register fields for HFGITR2_EL2
> > arm64/sysreg: Add register fields for HFGRTR2_EL2
> > arm64/sysreg: Add register fields for HFGWTR2_EL2
> > arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
>
> In case it is not clear, this series should be applied to 6.13 as the 2
> PMUv3p9 features already landed in 6.13 (per counter EL0 control) and
> 6.12 (ICNTR).
So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
counter")? It's pretty late in the cycle to take the series for 6.13.
But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
than traps it at EL2?
--
Catalin
On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> > On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > > being used in the kernel. This is required to prevent their EL1 access trap
> > > into EL2.
> > >
> > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > > for now as it does not get accessed in the kernel, and there is no plan for
> > > its access from user space.
> > >
> > > I have taken the liberty to pick up all the review tags for patches related
> > > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> > >
> > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> > >
> > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > > can be found here.
> > >
> > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> > >
> > > This series is based on v6.13-rc3
> > >
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: Marc Zyngier <maz@kernel.org>
> > > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: Mark Brown <robh@kernel.org>
> > > Cc: Rob Herring <robh@kernel.org>
> > > Cc: Oliver Upton <oliver.upton@linux.dev>
> > > Cc: Jonathan Corbet <corbet@lwn.net>
> > > Cc: Eric Auger <eric.auger@redhat.com>
> > > Cc: kvmarm@lists.linux.dev
> > > Cc: linux-doc@vger.kernel.org
> > > Cc: linux-kernel@vger.kernel.org
> > > Cc: linux-arm-kernel@lists.infradead.org
> > >
> > > Anshuman Khandual (7):
> > > arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> > > arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > > arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > > arm64/sysreg: Add register fields for HFGITR2_EL2
> > > arm64/sysreg: Add register fields for HFGRTR2_EL2
> > > arm64/sysreg: Add register fields for HFGWTR2_EL2
> > > arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
> >
> > In case it is not clear, this series should be applied to 6.13 as the 2
> > PMUv3p9 features already landed in 6.13 (per counter EL0 control) and
> > 6.12 (ICNTR).
>
> So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
> d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
> counter")? It's pretty late in the cycle to take the series for 6.13.
Ideally, yes. But given the state of h/w implementations, backporting
it later is probably fine if that is your preference.
> But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> than traps it at EL2?
As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
accesses to these registers are trapped with or without this series.
Rob
On Tue, 07 Jan 2025 22:13:47 +0000,
Rob Herring <robh@kernel.org> wrote:
>
> On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> >
> > On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> > > On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > > > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > > > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > > > being used in the kernel. This is required to prevent their EL1 access trap
> > > > into EL2.
> > > >
> > > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > > > for now as it does not get accessed in the kernel, and there is no plan for
> > > > its access from user space.
> > > >
> > > > I have taken the liberty to pick up all the review tags for patches related
> > > > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> > > >
> > > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> > > >
> > > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > > > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > > > can be found here.
> > > >
> > > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> > > >
> > > > This series is based on v6.13-rc3
> > > >
> > > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > > Cc: Will Deacon <will@kernel.org>
> > > > Cc: Marc Zyngier <maz@kernel.org>
> > > > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > > Cc: Mark Brown <robh@kernel.org>
> > > > Cc: Rob Herring <robh@kernel.org>
> > > > Cc: Oliver Upton <oliver.upton@linux.dev>
> > > > Cc: Jonathan Corbet <corbet@lwn.net>
> > > > Cc: Eric Auger <eric.auger@redhat.com>
> > > > Cc: kvmarm@lists.linux.dev
> > > > Cc: linux-doc@vger.kernel.org
> > > > Cc: linux-kernel@vger.kernel.org
> > > > Cc: linux-arm-kernel@lists.infradead.org
> > > >
> > > > Anshuman Khandual (7):
> > > > arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> > > > arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > > > arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > > > arm64/sysreg: Add register fields for HFGITR2_EL2
> > > > arm64/sysreg: Add register fields for HFGRTR2_EL2
> > > > arm64/sysreg: Add register fields for HFGWTR2_EL2
> > > > arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
> > >
> > > In case it is not clear, this series should be applied to 6.13 as the 2
> > > PMUv3p9 features already landed in 6.13 (per counter EL0 control) and
> > > 6.12 (ICNTR).
> >
> > So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
> > d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
> > counter")? It's pretty late in the cycle to take the series for 6.13.
>
> Ideally, yes. But given the state of h/w implementations, backporting
> it later is probably fine if that is your preference.
>
> > But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> > than traps it at EL2?
>
> As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
> accesses to these registers are trapped with or without this series.
And most probably generates a nice splat in the kernel log, as nobody
updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal
with the FGT2 registers.
M.
--
Without deviation from the norm, progress is not possible.
On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Tue, 07 Jan 2025 22:13:47 +0000,
> Rob Herring <robh@kernel.org> wrote:
> >
> > On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> > >
> > > On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> > > > On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > > > > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > > > > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > > > > being used in the kernel. This is required to prevent their EL1 access trap
> > > > > into EL2.
> > > > >
> > > > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > > > > for now as it does not get accessed in the kernel, and there is no plan for
> > > > > its access from user space.
> > > > >
> > > > > I have taken the liberty to pick up all the review tags for patches related
> > > > > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> > > > >
> > > > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> > > > >
> > > > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > > > > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > > > > can be found here.
> > > > >
> > > > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> > > > >
> > > > > This series is based on v6.13-rc3
> > > > >
> > > > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > > > Cc: Will Deacon <will@kernel.org>
> > > > > Cc: Marc Zyngier <maz@kernel.org>
> > > > > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > > > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > > > Cc: Mark Brown <robh@kernel.org>
> > > > > Cc: Rob Herring <robh@kernel.org>
> > > > > Cc: Oliver Upton <oliver.upton@linux.dev>
> > > > > Cc: Jonathan Corbet <corbet@lwn.net>
> > > > > Cc: Eric Auger <eric.auger@redhat.com>
> > > > > Cc: kvmarm@lists.linux.dev
> > > > > Cc: linux-doc@vger.kernel.org
> > > > > Cc: linux-kernel@vger.kernel.org
> > > > > Cc: linux-arm-kernel@lists.infradead.org
> > > > >
> > > > > Anshuman Khandual (7):
> > > > > arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> > > > > arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > > > > arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > > > > arm64/sysreg: Add register fields for HFGITR2_EL2
> > > > > arm64/sysreg: Add register fields for HFGRTR2_EL2
> > > > > arm64/sysreg: Add register fields for HFGWTR2_EL2
> > > > > arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
> > > >
> > > > In case it is not clear, this series should be applied to 6.13 as the 2
> > > > PMUv3p9 features already landed in 6.13 (per counter EL0 control) and
> > > > 6.12 (ICNTR).
> > >
> > > So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
> > > d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
> > > counter")? It's pretty late in the cycle to take the series for 6.13.
> >
> > Ideally, yes. But given the state of h/w implementations, backporting
> > it later is probably fine if that is your preference.
> >
> > > But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> > > than traps it at EL2?
> >
> > As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
> > accesses to these registers are trapped with or without this series.
>
> And most probably generates a nice splat in the kernel log, as nobody
> updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal
> with the FGT2 registers.
Isn't that this series[1]? Should that have come first, I guess I know
that *now*.
Out of curiosity, why do we care if there's a splat or not for a not
well behaved guest?
Rob
[1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
On Wed, Jan 08, 2025 at 07:47:16AM -0600, Rob Herring wrote: > On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote: > > On Tue, 07 Jan 2025 22:13:47 +0000, > > Rob Herring <robh@kernel.org> wrote: > > > On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote: > > > > But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and > > > > than traps it at EL2? > > > > > > As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest > > > accesses to these registers are trapped with or without this series. > > > > And most probably generates a nice splat in the kernel log, as nobody > > updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal > > with the FGT2 registers. > > Isn't that this series[1]? Should that have come first, I guess I know > that *now*. [...] > [1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/ It's not any clearer to me. Does this series depend on the 46-patch one? Or, if we had the other, is this no longer needed? Or none of these, they are independent. -- Catalin
On Thu, Jan 16, 2025 at 9:32 AM Catalin Marinas <catalin.marinas@arm.com> wrote: > > On Wed, Jan 08, 2025 at 07:47:16AM -0600, Rob Herring wrote: > > On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote: > > > On Tue, 07 Jan 2025 22:13:47 +0000, > > > Rob Herring <robh@kernel.org> wrote: > > > > On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote: > > > > > But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and > > > > > than traps it at EL2? > > > > > > > > As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest > > > > accesses to these registers are trapped with or without this series. > > > > > > And most probably generates a nice splat in the kernel log, as nobody > > > updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal > > > with the FGT2 registers. > > > > Isn't that this series[1]? Should that have come first, I guess I know > > that *now*. > [...] > > [1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/ > > It's not any clearer to me. Does this series depend on the 46-patch one? > Or, if we had the other, is this no longer needed? Or none of these, > they are independent. They are independent. I think ideally we'd want everything landing at the same time, but we're past ideal at this point. Without this series, if someone uses PMU on v8.9 and firmware enabled FGT2, then the kernel will crash. Without the above series, KVM will have warnings in the kernel log, but otherwise function. Rob
On 1/18/25 03:37, Rob Herring wrote: > On Thu, Jan 16, 2025 at 9:32 AM Catalin Marinas <catalin.marinas@arm.com> wrote: >> >> On Wed, Jan 08, 2025 at 07:47:16AM -0600, Rob Herring wrote: >>> On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote: >>>> On Tue, 07 Jan 2025 22:13:47 +0000, >>>> Rob Herring <robh@kernel.org> wrote: >>>>> On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote: >>>>>> But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and >>>>>> than traps it at EL2? >>>>> >>>>> As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest >>>>> accesses to these registers are trapped with or without this series. >>>> >>>> And most probably generates a nice splat in the kernel log, as nobody >>>> updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal >>>> with the FGT2 registers. >>> >>> Isn't that this series[1]? Should that have come first, I guess I know >>> that *now*. >> [...] >>> [1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/ >> >> It's not any clearer to me. Does this series depend on the 46-patch one? >> Or, if we had the other, is this no longer needed? Or none of these, >> they are independent. > > They are independent. I think ideally we'd want everything landing at > the same time, but we're past ideal at this point. Without this > series, if someone uses PMU on v8.9 and firmware enabled FGT2, then > the kernel will crash. Without the above series, KVM will have > warnings in the kernel log, but otherwise function. Right, they are independent. Just that Rob had observed this PMU v3.8 boot requirement while reviewing the HW breakpoint series earlier. I should just respin this series after the upcoming v6.14-rc1 release is out ?
On Tue, Jan 28, 2025 at 02:41:17PM +0530, Anshuman Khandual wrote: > On 1/18/25 03:37, Rob Herring wrote: > > On Thu, Jan 16, 2025 at 9:32 AM Catalin Marinas <catalin.marinas@arm.com> wrote: > >> > >> On Wed, Jan 08, 2025 at 07:47:16AM -0600, Rob Herring wrote: > >>> On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote: > >>>> On Tue, 07 Jan 2025 22:13:47 +0000, > >>>> Rob Herring <robh@kernel.org> wrote: > >>>>> On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote: > >>>>>> But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and > >>>>>> than traps it at EL2? > >>>>> > >>>>> As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest > >>>>> accesses to these registers are trapped with or without this series. > >>>> > >>>> And most probably generates a nice splat in the kernel log, as nobody > >>>> updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal > >>>> with the FGT2 registers. > >>> > >>> Isn't that this series[1]? Should that have come first, I guess I know > >>> that *now*. > >> [...] > >>> [1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/ > >> > >> It's not any clearer to me. Does this series depend on the 46-patch one? > >> Or, if we had the other, is this no longer needed? Or none of these, > >> they are independent. > > > > They are independent. I think ideally we'd want everything landing at > > the same time, but we're past ideal at this point. Without this > > series, if someone uses PMU on v8.9 and firmware enabled FGT2, then > > the kernel will crash. Without the above series, KVM will have > > warnings in the kernel log, but otherwise function. > > Right, they are independent. Just that Rob had observed this PMU v3.8 boot > requirement while reviewing the HW breakpoint series earlier. I should just > respin this series after the upcoming v6.14-rc1 release is out ? They may apply cleanly but please do rebase and repost at -rc1. Thanks. -- Catalin
On Wed, 08 Jan 2025 13:47:16 +0000, Rob Herring <robh@kernel.org> wrote: > > Out of curiosity, why do we care if there's a splat or not for a not > well behaved guest? The only well behaved guest is the one that doesn't run. Getting that splat is an indication of a *KVM* bug which fails to correctly emulate the architecture (feature not advertised -> instructions must silently UNDEF). M. -- Without deviation from the norm, progress is not possible.
On Tue, 07 Jan 2025 12:13:40 +0000,
Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> > On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > > being used in the kernel. This is required to prevent their EL1 access trap
> > > into EL2.
> > >
> > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > > for now as it does not get accessed in the kernel, and there is no plan for
> > > its access from user space.
> > >
> > > I have taken the liberty to pick up all the review tags for patches related
> > > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> > >
> > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> > >
> > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > > can be found here.
> > >
> > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> > >
> > > This series is based on v6.13-rc3
> > >
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: Marc Zyngier <maz@kernel.org>
> > > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: Mark Brown <robh@kernel.org>
> > > Cc: Rob Herring <robh@kernel.org>
> > > Cc: Oliver Upton <oliver.upton@linux.dev>
> > > Cc: Jonathan Corbet <corbet@lwn.net>
> > > Cc: Eric Auger <eric.auger@redhat.com>
> > > Cc: kvmarm@lists.linux.dev
> > > Cc: linux-doc@vger.kernel.org
> > > Cc: linux-kernel@vger.kernel.org
> > > Cc: linux-arm-kernel@lists.infradead.org
> > >
> > > Anshuman Khandual (7):
> > > arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> > > arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > > arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > > arm64/sysreg: Add register fields for HFGITR2_EL2
> > > arm64/sysreg: Add register fields for HFGRTR2_EL2
> > > arm64/sysreg: Add register fields for HFGWTR2_EL2
> > > arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
> >
> > In case it is not clear, this series should be applied to 6.13 as the 2
> > PMUv3p9 features already landed in 6.13 (per counter EL0 control) and
> > 6.12 (ICNTR).
>
> So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
> d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
> counter")? It's pretty late in the cycle to take the series for 6.13.
>
> But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> than traps it at EL2?
We limit the PMU emulation to v3p8, so *hopefully* this doesn't trip
anything in KVM, even if we don't advertise support for these
features. This has been tested, right?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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