From nobody Sun Feb 8 16:32:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1EB5D1A3BD7; Fri, 20 Dec 2024 07:22:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679381; cv=none; b=JenV3nO9EBJFl55oEfOqfz5YhWcGZgDahBBPWP4JJsaSA/tlrgIY8fCc1Ym9XGYddmIfnGcZf0bNNMaiB+sLBBDK1U7qazNLdnK6bOSzj8RsXMPrhHqhFL46jnNwNGNs5lJksQNQ2n+aXKXUb1DWNZCD3nU6zYmbDLtOVJKZyoM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679381; c=relaxed/simple; bh=Rv2fDgk3NSsy+yodD2WxigI/6HaXKujPQ+9sBsPdaWE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CAf20/ODd8oOfLP1PZjdSzbI+jXmZ6UKN803Rsdt2d3hXchSbBLEJaxDs3pVqr2qPG8wJZ2lR3q0ve2g1YfVwMbAFrDk0avUZuumHOevDdwFmbNAKGlSJeRVhl/QJ6Hbf3F2EUBLxS0lhbhJe5pWxMAeb1JBoifnZ1/OBQU3cnw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 92AC01596; Thu, 19 Dec 2024 23:23:27 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.51.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E98F03F58B; Thu, 19 Dec 2024 23:22:53 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Marc Zyngier , Ryan Roberts , Mark Rutland , Mark Brown , Oliver Upton , Jonathan Corbet , Eric Auger , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH 1/7] arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 Date: Fri, 20 Dec 2024 12:52:34 +0530 Message-Id: <20241220072240.1003352-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241220072240.1003352-1-anshuman.khandual@arm.com> References: <20241220072240.1003352-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64MMFR0_EL1 register fields as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b081b54d6d22..a6cbe0dcd63b 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1591,6 +1591,7 @@ EndEnum UnsignedEnum 59:56 FGT 0b0000 NI 0b0001 IMP + 0b0010 FGT2 EndEnum Res0 55:48 UnsignedEnum 47:44 EXS @@ -1652,6 +1653,7 @@ Enum 3:0 PARANGE 0b0100 44 0b0101 48 0b0110 52 + 0b0111 56 EndEnum EndSysreg =20 --=20 2.25.1 From nobody Sun Feb 8 16:32:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 540F319F11E; Fri, 20 Dec 2024 07:23:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679386; cv=none; b=pf0Ij1qJ6GnNFj4Xk3fPP0JchSbTmSL9F9eMOc3TYfkJPPRNCJq2Ifh2CJqudYXU3jy58sSjIqgvY+opp1JsepISnOIakS/nrTu+ZLSYTJudfhAFxcl1NS+z0OXd4rwBejjLX10ZvunDEIV1HaCFZc5vNGLMvd+QBeNx1SqQf+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679386; c=relaxed/simple; bh=lLUXm52vosQeXt5yShEHaPrDe3fijMXl7s6Uqnau8NE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SshIgxW6vHWex7TwnJX2SL++Tddq/5MpYzwJWiN/lt4bjUHnIwn7R9Pi7KSxzC5ShJkxoLnCimTQ7z3s1Er6GCWglyrMcGWJnDtKxU6Sbqv/+zuGXAYDUPHDUjMZ+kGU13ah6CVSm/zLgoyHKKfkb7ElPABJ10IGVswaFrZspoo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C7E501A00; Thu, 19 Dec 2024 23:23:32 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.51.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1363F3F58B; Thu, 19 Dec 2024 23:22:59 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Marc Zyngier , Ryan Roberts , Mark Rutland , Mark Brown , Oliver Upton , Jonathan Corbet , Eric Auger , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH 2/7] arm64/sysreg: Add register fields for HDFGRTR2_EL2 Date: Fri, 20 Dec 2024 12:52:35 +0530 Message-Id: <20241220072240.1003352-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241220072240.1003352-1-anshuman.khandual@arm.com> References: <20241220072240.1003352-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGRTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a6cbe0dcd63b..9ce8602dd40f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2546,6 +2546,35 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg =20 +Sysreg HDFGRTR2_EL2 3 4 3 1 0 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Res0 21 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Field 18 nSPMDEVAFF_EL1 +Field 17 nSPMID +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Field 6 nPMSSDATA +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Sun Feb 8 16:32:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 71DC91A0BCF; Fri, 20 Dec 2024 07:23:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679392; cv=none; b=Td3YyRnavwCVqxKqk6s5DjouJ+rqLXf9XI2HSBX91zyExUAnPWFjnpdkGOOWUWN72q2qSjPTWq0FHbmDUTpFDJOS4eXpTrdkV5QEjbi8zMrz0A9aMZRvHNJudaGppNsYL+hsZSuITsMa/SC/n/xLSBB+TdzqVAsVcxQ1NbtUs34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679392; c=relaxed/simple; bh=nIceMfvuW4qySkg0J3rYWDUEk38BwWSRTy6dngdXqQ4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SKYOxfvBJ+k3rvQLeifW7d72gW9A4dJuYHPnHzR55z/Fdk0FzwfXJo6ppjo5WsA9xlSeYUiWFFPjgyVPofP14JvO6MabVSr9aM8y8Kl1BHUWlRyv1NX2PXS4NOXbuZITiSAO6tEyEf3ihaeJwQVFv4yZiZXSPwR9hwcXozjZhQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0CFBD1E32; Thu, 19 Dec 2024 23:23:38 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.51.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4990B3F58B; Thu, 19 Dec 2024 23:23:05 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Marc Zyngier , Ryan Roberts , Mark Rutland , Mark Brown , Oliver Upton , Jonathan Corbet , Eric Auger , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH 3/7] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Date: Fri, 20 Dec 2024 12:52:36 +0530 Message-Id: <20241220072240.1003352-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241220072240.1003352-1-anshuman.khandual@arm.com> References: <20241220072240.1003352-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGWTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 9ce8602dd40f..f5a1fa75ec72 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2575,6 +2575,34 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg =20 +Sysreg HDFGWTR2_EL2 3 4 3 1 1 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Field 21 nPMZR_EL0 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Res0 18:17 +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Res0 6 +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Sun Feb 8 16:32:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C08B71A3AB1; Fri, 20 Dec 2024 07:23:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679397; cv=none; b=gkdgDlvV+irAPPaIjOKGeJwoxLqIcOdFyx3KH4Xx71VS5DfgVnDRjryGzbZGWscKmue+tbdnn86Vt8/V4AP/jMTWAOlLTgAw2Lf7QjkB5OMkZs6cs5d1NouQ/EHebSJEhyy9g7rL9GNyoyO5EqOWDXlpGd/OKz1Ng/4W8tUINtc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679397; c=relaxed/simple; bh=/VZ/frT5rATRiXvPDHxWosTrylF/qms8PLH5rYm70l4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dVilM2QOPijUz6ohyk87NQl8nm5DnkApBKbGItbUD2Kk+l/CYvfpUruTXzjDlD8rRa+pYnnWLZJzQjmQb6ku6b21lWEv8hbTKMDjWa9SOcUnuUuFpirIwGXRojmlhWsiKO5EYKrjNkH9dNB/L0xw8INo14QqWp/Dfeg6uto5c/c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6D88D1E5E; Thu, 19 Dec 2024 23:23:43 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.51.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 993A53F58B; Thu, 19 Dec 2024 23:23:10 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Marc Zyngier , Ryan Roberts , Mark Rutland , Mark Brown , Oliver Upton , Jonathan Corbet , Eric Auger , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH 4/7] arm64/sysreg: Add register fields for HFGITR2_EL2 Date: Fri, 20 Dec 2024 12:52:37 +0530 Message-Id: <20241220072240.1003352-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241220072240.1003352-1-anshuman.khandual@arm.com> References: <20241220072240.1003352-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HFGITR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index f5a1fa75ec72..088e3be8f884 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2775,6 +2775,12 @@ Field 1 AMEVCNTR00_EL0 Field 0 AMCNTEN0 EndSysreg =20 +Sysreg HFGITR2_EL2 3 4 3 1 7 +Res0 63:2 +Field 1 nDCCIVAPS +Field 0 TSBCSYNC +EndSysreg + Sysreg ZCR_EL2 3 4 1 2 0 Fields ZCR_ELx EndSysreg --=20 2.25.1 From nobody Sun Feb 8 16:32:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D05B41A7044; Fri, 20 Dec 2024 07:23:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679402; cv=none; b=daC8nTAxLPvmadsGFnP+bYCtF3zImVhUyxjVaL4H4mGn9K7dBqBUGOfZckBdqYCGnwYRYj3fvyGw4aorz3cM23SNmOcgR+VnfrobF3OQGkcvtrKSFlsB/4/j5r4TPTHDapPJQTUEXa7U344ycoOy2sQJRyzOOHx6h1TMtOFUazk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679402; c=relaxed/simple; bh=bv6IZ1p6mSqoqcSp8yKSomJ3PJRycgzTbltohfu1nIs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I5qNuJabr7y8YiMlXcBmt1vM8VvtDP5fHclKRWfLnNe/AEYpOVrkQ8erCih/PybsVz8frF9YHQAJVwF3H3XB5KgCf5g2pHs648a+0DzuW3WpI5qcxDQvPlPZmDpVnG/QIwTzaRA3BWCM8B8s0Q1laGhPaOLjTtsS3Xbhi0E6NIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 96F031E7D; Thu, 19 Dec 2024 23:23:48 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.51.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E28133F58B; Thu, 19 Dec 2024 23:23:15 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Marc Zyngier , Ryan Roberts , Mark Rutland , Mark Brown , Oliver Upton , Jonathan Corbet , Eric Auger , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH 5/7] arm64/sysreg: Add register fields for HFGRTR2_EL2 Date: Fri, 20 Dec 2024 12:52:38 +0530 Message-Id: <20241220072240.1003352-6-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241220072240.1003352-1-anshuman.khandual@arm.com> References: <20241220072240.1003352-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HFGRTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 088e3be8f884..0875e0057706 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2603,6 +2603,25 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg =20 +Sysreg HFGRTR2_EL2 3 4 3 1 2 +Res0 63:15 +Field 14 nACTLRALIAS_EL1 +Field 13 nACTLRMASK_EL1 +Field 12 nTCR2ALIAS_EL1 +Field 11 nTCRALIAS_EL1 +Field 10 nSCTLRALIAS2_EL1 +Field 9 nSCTLRALIAS_EL1 +Field 8 nCPACRALIAS_EL1 +Field 7 nTCR2MASK_EL1 +Field 6 nTCRMASK_EL1 +Field 5 nSCTLR2MASK_EL1 +Field 4 nSCTLRMASK_EL1 +Field 3 nCPACRMASK_EL1 +Field 2 nRCWSMASK_EL1 +Field 1 nERXGSR_EL1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Sun Feb 8 16:32:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 42FB71A83E0; Fri, 20 Dec 2024 07:23:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679409; cv=none; b=GD5q+Z8YcQ4qCfjk8lTu65Dp0fZWRki/2lokVZfjigRwincQ0kLTvWy7Gy0pkGtx0/fOVMdEnjduYUuzmCxgK3wR/FFD9FE1IRviRT0Bcg7i79tvjHERwOIWxC/SJN5zQk3OT1yB1Wf0uA5pCI49651+Eo/SPP2nI0XVUIpCUOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679409; c=relaxed/simple; bh=5hDOVsWv26kg/q9N1eUVGt8sjdaaZ4GI2zjybAoJLSg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Aq/0FexU/5TKYUx9gY/EEN0h/JVcWNaWIL+SLo7VfHzmuYPydrbEC1rbbO04dHVl9mXiOs24QjHmRaDFLP1L1/wJf2sTZ5tAMVdjTFOBME2KxO5zojgqD7W17rX2Qlta+lf365hizXek8o9uCMSU+YcRHwV3R9LXtVS88cv/HV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DA3F81E8D; Thu, 19 Dec 2024 23:23:53 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.51.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 172B13F58B; Thu, 19 Dec 2024 23:23:20 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Marc Zyngier , Ryan Roberts , Mark Rutland , Mark Brown , Oliver Upton , Jonathan Corbet , Eric Auger , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH 6/7] arm64/sysreg: Add register fields for HFGWTR2_EL2 Date: Fri, 20 Dec 2024 12:52:39 +0530 Message-Id: <20241220072240.1003352-7-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241220072240.1003352-1-anshuman.khandual@arm.com> References: <20241220072240.1003352-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HFGWTR2_EL2 as per the definitions based on DDI0601 2024-09. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0875e0057706..268f1b808e3f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2622,6 +2622,25 @@ Field 1 nERXGSR_EL1 Field 0 nPFAR_EL1 EndSysreg =20 +Sysreg HFGWTR2_EL2 3 4 3 1 3 +Res0 63:15 +Field 14 nACTLRALIAS_EL1 +Field 13 nACTLRMASK_EL1 +Field 12 nTCR2ALIAS_EL1 +Field 11 nTCRALIAS_EL1 +Field 10 nSCTLRALIAS2_EL1 +Field 9 nSCTLRALIAS_EL1 +Field 8 nCPACRALIAS_EL1 +Field 7 nTCR2MASK_EL1 +Field 6 nTCRMASK_EL1 +Field 5 nSCTLR2MASK_EL1 +Field 4 nSCTLRMASK_EL1 +Field 3 nCPACRMASK_EL1 +Field 2 nRCWSMASK_EL1 +Res0 1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Sun Feb 8 16:32:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5A5CA1B041E; Fri, 20 Dec 2024 07:23:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679413; cv=none; b=pTUzAI325hlfzxVgjCpPU+RFF0EBeBNBYCSa3u2MVIajuVhkWgWV05Z8c5eSe2+ZwzoeQN2ZWEk3ngKwPfwzcU2tK8d+w3UFI0AoM20U3RXe0JDxrp4MMIi1oUYRekGB6GywNrXOCu4ltsza431ZS4zrJ0DCQ2qJW1+8E3Cu3/U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734679413; c=relaxed/simple; bh=4DdM2+nm65X+iCfqvXi65Xkv7UQylGOacyvdeRuSj4k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=T3PRkrYi7zxfSS9OtY8DpRBEPtifwDzn3KbGl3cLBn6FQlLSG5bWdDeyMHl8UmHwPdTo89QZg4g9BOBohRvEtJu/2QI5EmzX4+h1tBUdTfYPSam8N9yUvTPEj/yG57xYd6H1rCz2AIwIa/shSwCn3UnsMxPrSD5yW0WTDtuyZIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CD9971EA6; Thu, 19 Dec 2024 23:23:58 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.51.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5A45E3F58B; Thu, 19 Dec 2024 23:23:26 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Marc Zyngier , Ryan Roberts , Mark Rutland , Mark Brown , Oliver Upton , Jonathan Corbet , Eric Auger , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 Date: Fri, 20 Dec 2024 12:52:40 +0530 Message-Id: <20241220072240.1003352-8-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241220072240.1003352-1-anshuman.khandual@arm.com> References: <20241220072240.1003352-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" FEAT_PMUv3p9 registers such as PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 access from EL1 requires appropriate EL2 fine grained trap configuration via FEAT_FGT2 based trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2. Otherwise such register accesses will result in traps into EL2. Add a new helper __init_el2_fgt2() which initializes FEAT_FGT2 based fine grained trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2 (setting the bits nPMICNTR_EL0, nPMICFILTR_EL0 and nPMUACR_EL1) to enable access into PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 registers. Also update booting.rst with SCR_EL3.FGTEn2 requirement for all FEAT_FGT2 based registers to be accessible in EL2. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: Rob Herring Cc: Jonathan Corbet Cc: Marc Zyngier Cc: Oliver Upton Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: kvmarm@lists.linux.dev Signed-off-by: Anshuman Khandual Reviewed-by: Rob Herring (Arm) Tested-by: Rob Herring (Arm) --- Documentation/arch/arm64/booting.rst | 18 ++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 25 +++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm6= 4/booting.rst index 3278fb4bf219..57ca46577084 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -288,6 +288,12 @@ Before jumping into the kernel, the following conditio= ns must be met: =20 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. =20 + For CPUs with the Fine Grained Traps 2 (FEAT_FGT2) extension present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present: =20 - If EL3 is present and the kernel is entered at EL2: @@ -382,6 +388,18 @@ Before jumping into the kernel, the following conditio= ns must be met: =20 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. =20 + For CPUs with the Performance Monitors Extension (FEAT_PMUv3p9): + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1. + - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. + - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. + + - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1. + - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. + - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. + For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): =20 - If the kernel is entered at EL1 and EL2 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 4ef52d7245bb..9e44c13711e5 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -233,6 +233,30 @@ .Lskip_fgt_\@: .endm =20 +.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_\@ + + mov x0, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 + b.lt .Lskip_pmuv3p9_\@ + + orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 + orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 + orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 +.Lskip_pmuv3p9_\@: + msr_s SYS_HDFGRTR2_EL2, x0 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HFGRTR2_EL2, xzr + msr_s SYS_HFGWTR2_EL2, xzr + msr_s SYS_HFGITR2_EL2, xzr +.Lskip_fgt2_\@: +.endm + .macro __init_el2_gcs mrs_s x1, SYS_ID_AA64PFR1_EL1 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 @@ -283,6 +307,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 __init_el2_gcs .endm =20 --=20 2.25.1