[PATCH v2 0/5] Add Apple SPI controller and spi-nor dt nodes

Janne Grunau via B4 Relay posted 5 patches 1 year ago
arch/arm64/boot/dts/apple/spi1-nvram.dtsi      | 39 +++++++++++++
arch/arm64/boot/dts/apple/t600x-common.dtsi    |  7 +++
arch/arm64/boot/dts/apple/t600x-die0.dtsi      | 28 ++++++++++
arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi | 14 +++++
arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi |  2 +
arch/arm64/boot/dts/apple/t600x-j375.dtsi      |  2 +
arch/arm64/boot/dts/apple/t8103-jxxx.dtsi      |  2 +
arch/arm64/boot/dts/apple/t8103-pmgr.dtsi      | 18 +++---
arch/arm64/boot/dts/apple/t8103.dtsi           | 76 ++++++++++++++++++++++++++
arch/arm64/boot/dts/apple/t8112-jxxx.dtsi      |  2 +
arch/arm64/boot/dts/apple/t8112.dtsi           | 44 ++++++++++++++-
11 files changed, 224 insertions(+), 10 deletions(-)
[PATCH v2 0/5] Add Apple SPI controller and spi-nor dt nodes
Posted by Janne Grunau via B4 Relay 1 year ago
This series adds SPI controller and SPI NOR flash device nodes to the
man Apple silicon SoC dts files. Only the subset of used SPI controllers
is added. Five SPI controllers exists according to pmgr ADT data but the
commits only add controllers found in use on any of the devices. The
parameters for the missing nodes are guessable but there's no point in
adding them since no further M1 or M2 devices are expected.
Together with controller nodes the first SPI device is added. All Apple
silicon devices connect a SPI NOR flash to spi1. This holds Apple's 1st
stage bootloader, firmwares, platform and machine specific config data
and a writeable key-value store (nvram). Expose only the nvram as mtd
partition since it has use beyond exploring the content. Tools from
asahi-nvram [1] can modify the (default) boot configuration
(asahi-bless), read Bluetooth sync keys (asahi-btsync) and read and
write arbitrary keys (asahi-nvram).

Devicetree bindings are included in the driver series. Last version at
https://lore.kernel.org/linux-devicetree/20241101-asahi-spi-v3-0-3b411c5fb8e5@jannau.net/

This series passes `make CHECK_DTBS=1 dtbs` with the spi bindings except
for "local-mac-address" for the Bluetooth device (I need get back to
this).

[1] https://github.com/WhatAmISupposedToPutHere/asahi-nvram/

Signed-off-by: Janne Grunau <j@jannau.net>
---
Changes in v2:
- added spi0 pins from https://lore.kernel.org/asahi/969b7440-5173-4ecc-af31-c3cd1f3f5acf@marcan.st/
- rebased onto v6.13-rc1
- added Neal's Rb:
- Link to v1: https://lore.kernel.org/r/20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net
              https://lore.kernel.org/r/20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net

---
Hector Martin (1):
      arm64: dts: apple: t8103: Fix spi4 power domain sort order

Janne Grunau (4):
      arm64: dts: apple: t8103: Add spi controller nodes
      arm64: dts: apple: t8112: Add spi controller nodes
      arm64: dts: apple: t600x: Add spi controller nodes
      arm64: dts: apple: Add SPI NOR nvram partition to all devices

 arch/arm64/boot/dts/apple/spi1-nvram.dtsi      | 39 +++++++++++++
 arch/arm64/boot/dts/apple/t600x-common.dtsi    |  7 +++
 arch/arm64/boot/dts/apple/t600x-die0.dtsi      | 28 ++++++++++
 arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi | 14 +++++
 arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi |  2 +
 arch/arm64/boot/dts/apple/t600x-j375.dtsi      |  2 +
 arch/arm64/boot/dts/apple/t8103-jxxx.dtsi      |  2 +
 arch/arm64/boot/dts/apple/t8103-pmgr.dtsi      | 18 +++---
 arch/arm64/boot/dts/apple/t8103.dtsi           | 76 ++++++++++++++++++++++++++
 arch/arm64/boot/dts/apple/t8112-jxxx.dtsi      |  2 +
 arch/arm64/boot/dts/apple/t8112.dtsi           | 44 ++++++++++++++-
 11 files changed, 224 insertions(+), 10 deletions(-)
---
base-commit: 40384c840ea1944d7c5a392e8975ed088ecf0b37
change-id: 20241101-asahi-spi-dt-58245bb1da3e

Best regards,
-- 
Janne Grunau <j@jannau.net>
Re: [PATCH v2 0/5] Add Apple SPI controller and spi-nor dt nodes
Posted by Sven Peter 10 months ago
On Tue, 03 Dec 2024 08:57:56 +0100, Janne Grunau wrote:
> This series adds SPI controller and SPI NOR flash device nodes to the
> man Apple silicon SoC dts files. Only the subset of used SPI controllers
> is added. Five SPI controllers exists according to pmgr ADT data but the
> commits only add controllers found in use on any of the devices. The
> parameters for the missing nodes are guessable but there's no point in
> adding them since no further M1 or M2 devices are expected.
> Together with controller nodes the first SPI device is added. All Apple
> silicon devices connect a SPI NOR flash to spi1. This holds Apple's 1st
> stage bootloader, firmwares, platform and machine specific config data
> and a writeable key-value store (nvram). Expose only the nvram as mtd
> partition since it has use beyond exploring the content. Tools from
> asahi-nvram [1] can modify the (default) boot configuration
> (asahi-bless), read Bluetooth sync keys (asahi-btsync) and read and
> write arbitrary keys (asahi-nvram).
> 
> [...]

Applied, thanks!

[1/5] arm64: dts: apple: t8103: Fix spi4 power domain sort order
      commit: 1f7af2931158a5e819ac71bcba91e961ac5ca3ea
[2/5] arm64: dts: apple: t8103: Add spi controller nodes
      commit: 556cd4bbb45bb5a73042c02b7e5c982112a6ed1f
[3/5] arm64: dts: apple: t8112: Add spi controller nodes
      commit: 0a6d561c7e46bf46b886af209e8ebedb6d500680
[4/5] arm64: dts: apple: t600x: Add spi controller nodes
      commit: d08e455a865c99a8050addf4dc001bcfdf1b7b8b
[5/5] arm64: dts: apple: Add SPI NOR nvram partition to all devices
      commit: 3febe9de5ca5267618675650871a626d0901f8cb

Best regards,
-- 
Sven Peter <sven@svenpeter.dev>