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Tue, 3 Dec 2024 07:58:04 +0000 (UTC) From: Janne Grunau via B4 Relay Date: Tue, 03 Dec 2024 08:57:57 +0100 Subject: [PATCH v2 1/5] arm64: dts: apple: t8103: Fix spi4 power domain sort order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241203-asahi-spi-dt-v2-1-cd68bfaf0c84@jannau.net> References: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> In-Reply-To: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Neal Gompa X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1498; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=9ueUveKszfxawJ0HmIK5r7NU/tiqsgQwLWeRgQUwJgA=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS/XVzVerG/X+kfvlZww+imQce2syrbvpnIbtvpz56tZ vDJ+VB0RykLgxgXg6yYIkuS9ssOhtU1ijG1D8Jg5rAygQxh4OIUgIlYSDIyHPl49dl3Zm+x2wZi F805WX4WfJtdxqR3LNIvlq1wkur2JEaGc9fKjx5hnDRx69rqxinMh1dsCmZbx+YgNvU3u8+FXav /sgEA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Hector Martin Signed-off-by: Hector Martin Reviewed-by: Neal Gompa --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t8103-pmgr.dtsi index 9645861a858c1a7c46c25a614c2cc4b03083bf46..c41c57d63997a59a9fe3c88de31= fddb31781398e 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -387,6 +387,15 @@ ps_spi3: power-controller@258 { power-domains =3D <&ps_sio>, <&ps_spi_p>; }; =20 + ps_spi4: power-controller@260 { + compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi4"; + power-domains =3D <&ps_sio>, <&ps_spi_p>; + }; + ps_uart_n: power-controller@268 { compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg =3D <0x268 4>; @@ -558,15 +567,6 @@ ps_mcc: power-controller@2f8 { apple,always-on; /* Memory controller */ }; =20 - ps_spi4: power-controller@260 { - compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg =3D <0x260 4>; - #power-domain-cells =3D <0>; - #reset-cells =3D <0>; - label =3D "spi4"; - power-domains =3D <&ps_sio>, <&ps_spi_p>; - }; - ps_dcs0: power-controller@300 { compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg =3D <0x300 4>; --=20 2.47.0 From nobody Fri Dec 19 22:05:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EE271D9A63; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241203-asahi-spi-dt-v2-2-cd68bfaf0c84@jannau.net> References: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> In-Reply-To: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Neal Gompa X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3632; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=9MFJ0ZiYLZ8Qk0zHZWVIFqmiPpB2dmJwF7SezS0P754=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS/XVyOh+tNdlx0U+S8GPvusdbXNZwXHgglMFxhD3q+/ NTt2w/EO0pZGMS4GGTFFFmStF92MKyuUYypfRAGM4eVCWQIAxenAExEPJfhf3nC44ld7R5hb698 O5WTHdFteWlJLN8E85Ubr9k0f1fwvcTwi0lL3nRCJH+t4LNleYb/VI+pMat1qQvXrlkXdYOXXyq LHQA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/t8103.dtsi | 76 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index 9b0dad6b618444ac6b1c9735c50cccfc3965f947..c9b789a2ff7e1757930b3fc3682= e734c1e4dbef9 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -326,6 +326,20 @@ clkref: clock-ref { clock-output-names =3D "clkref"; }; =20 + clk_120m: clock-120m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <120000000>; + clock-output-names =3D "clk_120m"; + }; + + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -441,6 +455,48 @@ fpwm1: pwm@235044000 { status =3D "disabled"; }; =20 + spi0: spi@235100000 { + compatible =3D "apple,t8103-spi", "apple,spi"; + reg =3D <0x2 0x35100000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi0_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@235104000 { + compatible =3D "apple,t8103-spi", "apple,spi"; + reg =3D <0x2 0x35104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@23510c000 { + compatible =3D "apple,t8103-spi", "apple,spi"; + reg =3D <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_120m>; + pinctrl-0 =3D <&spi3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + serial0: serial@235200000 { compatible =3D "apple,s5l-uart"; reg =3D <0x2 0x35200000 0x0 0x1000>; @@ -597,6 +653,26 @@ i2c4_pins: i2c4-pins { ; }; =20 + spi0_pins: spi0-pins { + pinmux =3D , /* CLK */ + , /* MOSI */ + ; /* MISO */ + }; + + spi1_pins: spi1-pins { + pinmux =3D , + , + , + ; + }; + + spi3_pins: spi3-pins { + pinmux =3D , + , + , + ; + }; + pcie_pins: pcie-pins { pinmux =3D , , --=20 2.47.0 From nobody Fri Dec 19 22:05:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E50D1D86DC; Tue, 3 Dec 2024 07:58:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733212685; cv=none; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241203-asahi-spi-dt-v2-3-cd68bfaf0c84@jannau.net> References: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> In-Reply-To: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Neal Gompa X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2929; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=AHySIPwyOhxDcF5B5Lzvbynlqb4i9BPBB11Y3mPxE4A=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS/XVzn3NQCKjdNN0yfwnZ7UpHptNoJ1xvCUvKub33Zt /OxhseSjlIWBjEuBlkxRZYk7ZcdDKtrFGNqH4TBzGFlAhnCwMUpABPZq8TIMOlxywQ/nzt9UUt1 KzvkjjJs7La63MK/THbP2Ts7OmboLGFk6Pp7i82f/V/RHxujqVy+yqYP97Cl719WMKvR9FvbcXd nfgA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/t8112.dtsi | 44 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/app= le/t8112.dtsi index 1666e6ab250bc0be9b8318e3c8fc903ccd3f3760..58d88f1ef92a32061765bd3b569= fdae0255dcd7e 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -349,6 +349,13 @@ clkref: clock-ref { clock-output-names =3D "clkref"; }; =20 + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -467,6 +474,34 @@ fpwm1: pwm@235044000 { status =3D "disabled"; }; =20 + spi1: spi@235104000 { + compatible =3D "apple,t8112-spi", "apple,spi"; + reg =3D <0x2 0x35104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@23510c000 { + compatible =3D "apple,t8112-spi", "apple,spi"; + reg =3D <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clkref>; + pinctrl-0 =3D <&spi3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + serial0: serial@235200000 { compatible =3D "apple,s5l-uart"; reg =3D <0x2 0x35200000 0x0 0x1000>; @@ -626,13 +661,20 @@ i2c4_pins: i2c4-pins { ; }; =20 - spi3_pins: spi3-pins { + spi1_pins: spi1-pins { pinmux =3D , , , ; }; =20 + spi3_pins: spi3-pins { + pinmux =3D , + , + , + ; + }; + pcie_pins: pcie-pins { pinmux =3D , , --=20 2.47.0 From nobody Fri Dec 19 22:05:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DC891DAC9B; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241203-asahi-spi-dt-v2-4-cd68bfaf0c84@jannau.net> References: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> In-Reply-To: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Neal Gompa X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3587; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=0IOE/oeGR4/UyYbOobtI6bLuT1HdoZECpY8ZAr7l87o=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS/XVz1ev2nL4cJ2n50yqm5H9One/jcBP8dB18WzWnOW LhMZYJrRykLgxgXg6yYIkuS9ssOhtU1ijG1D8Jg5rAygQxh4OIUgIks38zwv6hzpdEmgbh++eRn KZ9Cdk+P8Iif3V8yO3/bNYvyJzdKrjL8s+NQPT79kda9LV42seGKc98w28ze/1n2z5PUZaFmd3k OcwMA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/t600x-common.dtsi | 7 +++++++ arch/arm64/boot/dts/apple/t600x-die0.dtsi | 28 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi | 14 +++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-common.dtsi b/arch/arm64/boot/= dts/apple/t600x-common.dtsi index fa8ead69936366999786cdd4910266ee08b5ca7a..87dfc13d74171f62bf308740191= 8d9d41eaac560 100644 --- a/arch/arm64/boot/dts/apple/t600x-common.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-common.dtsi @@ -362,6 +362,13 @@ clkref: clock-ref { clock-output-names =3D "clkref"; }; =20 + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dt= s/apple/t600x-die0.dtsi index b1c875e692c8fb9c0af46a23568a7b0cd720141b..e9b3140ba1a996eeb91b3f60470= 833060b632bd2 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -163,6 +163,34 @@ i2c5: i2c@39b054000 { status =3D "disabled"; }; =20 + spi1: spi@39b104000 { + compatible =3D "apple,t6000-spi", "apple,spi"; + reg =3D <0x3 0x9b104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + status =3D "disabled"; + }; + + spi3: spi@39b10c000 { + compatible =3D "apple,t6000-spi", "apple,spi"; + reg =3D <0x3 0x9b10c000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkref>; + pinctrl-0 =3D <&spi3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi3>; + status =3D "disabled"; + }; + serial0: serial@39b200000 { compatible =3D "apple,s5l-uart"; reg =3D <0x3 0x9b200000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi b/arch/arm64/bo= ot/dts/apple/t600x-gpio-pins.dtsi index b31f1a7a2b3fc36e7dfa480d27012d6d0fd56f97..1a994c3c1b79f088d685e13d1dc= 16e7d1e6546f4 100644 --- a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi @@ -36,6 +36,20 @@ i2c5_pins: i2c5-pins { ; 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Tue, 3 Dec 2024 07:58:04 +0000 (UTC) From: Janne Grunau via B4 Relay Date: Tue, 03 Dec 2024 08:58:01 +0100 Subject: [PATCH v2 5/5] arm64: dts: apple: Add SPI NOR nvram partition to all devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241203-asahi-spi-dt-v2-5-cd68bfaf0c84@jannau.net> References: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> In-Reply-To: <20241203-asahi-spi-dt-v2-0-cd68bfaf0c84@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Neal Gompa X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3548; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=goZjmxtaAm4HRqmqPpfUIxijslYo2LoyehKKAI0aD84=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS/XVznGWaGH3g0JaF9w6nXjSLmM+ZllfyqPXDlqfZNn ceJn2qsOkpZGMS4GGTFFFmStF92MKyuUYypfRAGM4eVCWQIAxenAEzEdifDX4mlF05ka9zblx+d 8c+lIVXj46YnRyQ3/WyrM+oy7Cq5epOR4XeZ4Dk53f9K3+9cDnWv+f9UfOFCO1leltAZaz6bnZ1 ylRcA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau All known M1* and M2* devices use an identical SPI NOR flash configuration with a partition containing a non-volatile key:value storage. Use a .dtsi and include it for every device. The nvram partition parameters itself depend on the version of the installed Apple iboot boot loader. m1n1 will fill in the current values provided by Apple's iboot. Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/spi1-nvram.dtsi | 39 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 2 ++ arch/arm64/boot/dts/apple/t600x-j375.dtsi | 2 ++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 2 ++ arch/arm64/boot/dts/apple/t8112-jxxx.dtsi | 2 ++ 5 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/apple/spi1-nvram.dtsi b/arch/arm64/boot/dt= s/apple/spi1-nvram.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..3df2fd3993b52884d7c00b65099= c88d830a7a4c3 --- /dev/null +++ b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Devicetree include for common spi-nor nvram flash. +// +// Apple uses a consistent configiguration for the nvram on all known M1* = and +// M2* devices. +// +// Copyright The Asahi Linux Contributors + +/ { + aliases { + nvram =3D &nvram; + }; +}; + +&spi1 { + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-max-frequency =3D <25000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + nvram: partition@700000 { + label =3D "nvram"; + /* To be filled by the loader */ + reg =3D <0x0 0x0>; + status =3D "disabled"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/bo= ot/dts/apple/t600x-j314-j316.dtsi index 2e471dfe43cf885c1234d36bf0e0acfdc4904621..22ebc78e120bf8f0f71fd532e9d= ce4dcd117bbc6 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -119,3 +119,5 @@ sdhci0: mmc@0,0 { &fpwm0 { status =3D "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dt= s/apple/t600x-j375.dtsi index 1e5a19e49b089d4b3c5e12828b682d1993e35e75..d5b985ad567936111ee5cccc9ca= 9fc23d01d9edf 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -126,3 +126,5 @@ &pcie0_dart_2 { &pcie0_dart_3 { status =3D "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8103-jxxx.dtsi index 5988a4eb6efaa008c290b1842e0da2aae8052ba4..8e82231acab59ca0bffdcecfb66= 81f59661fcd96 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -90,3 +90,5 @@ bluetooth0: bluetooth@0,1 { &nco_clkref { clock-frequency =3D <900000000>; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8112-jxxx.dtsi index f5edf61113e7aa869613d672b281f7b7e84efb79..6da35496a4c88dbaba125ebbe8c= 5a4a428c647c3 100644 --- a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi @@ -79,3 +79,5 @@ &i2c3 { &nco_clkref { clock-frequency =3D <900000000>; }; + +#include "spi1-nvram.dtsi" --=20 2.47.0