Display port controller on some MSM chipsets are capable of supporting
multiple streams. In order to distinguish the streams better, describe
the current pixel clock better to emphasize that it drives the stream 0.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
---
 Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index a212f335d5ff..35ae2630c2b3 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -55,7 +55,7 @@ properties:
       - description: Display Port AUX clock
       - description: Display Port Link clock
       - description: Link interface clock between DP and PHY
-      - description: Display Port Pixel clock
+      - description: Display Port stream 0 Pixel clock
 
   clock-names:
     items:
@@ -68,7 +68,7 @@ properties:
   assigned-clocks:
     items:
       - description: link clock source
-      - description: pixel clock source
+      - description: stream 0 pixel clock source
 
   assigned-clock-parents:
     items:

-- 
2.34.1

On 03/12/2024 04:31, Abhinav Kumar wrote:
> Display port controller on some MSM chipsets are capable of supporting
> multiple streams. In order to distinguish the streams better, describe
> the current pixel clock better to emphasize that it drives the stream 0.
> 
This should be squashed with patch adding stream 1.

Best regards,
Krzysztof