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In order to distinguish the streams better, describe the current pixel clock better to emphasize that it drives the stream 0. Signed-off-by: Abhinav Kumar --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index a212f335d5ff..35ae2630c2b3 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -55,7 +55,7 @@ properties: - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - - description: Display Port Pixel clock + - description: Display Port stream 0 Pixel clock =20 clock-names: items: @@ -68,7 +68,7 @@ properties: assigned-clocks: items: - description: link clock source - - description: pixel clock source + - description: stream 0 pixel clock source =20 assigned-clock-parents: items: --=20 2.34.1