VOP2 support for RK3588 SoC is currently not capable to handle the full
range of display modes advertised by the connected screens, e.g. it
doesn't cope well with non-integer refresh rates like 59.94, 29.97,
23.98, etc.

There are two HDMI PHYs available on RK3588, each providing a PLL that
can be used by three out of the four VOP2 video ports as an alternative
and more accurate pixel clock source. This is able to correctly handle
all display modes up to 4K@60Hz.

As for the moment HDMI1 output is not supported upstream, the patch
series targets HDMI0 only.

Additionally, note that testing any HDMI 2.0 specific modes, e.g.
4K@60Hz, requires high TMDS clock ratio and scrambling support [1]. The
patch is usable but not yet ready to be submitted - I will handle this
soon.

Thanks,
Cristian

[1] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commits/rk3588-hdmi-bridge-next-20241115

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
Cristian Ciocaltea (5):
      dt-bindings: display: vop2: Add optional PLL clock properties
      drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation
      drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0
      arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
      arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588

 .../bindings/display/rockchip/rockchip-vop2.yaml   |  4 +++
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi      |  7 +++--
 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c       | 36 +++++++++++++++++++++-
 3 files changed, 44 insertions(+), 3 deletions(-)
---
base-commit: 744cf71b8bdfcdd77aaf58395e068b7457634b2c
change-id: 20241116-vop2-hdmi0-disp-modes-b39e3619768f

Hi,

On 11/17/24 03:22, Cristian Ciocaltea wrote:
> VOP2 support for RK3588 SoC is currently not capable to handle the full
> range of display modes advertised by the connected screens, e.g. it
> doesn't cope well with non-integer refresh rates like 59.94, 29.97,
> 23.98, etc.
> 
> There are two HDMI PHYs available on RK3588, each providing a PLL that
> can be used by three out of the four VOP2 video ports as an alternative
> and more accurate pixel clock source. This is able to correctly handle
> all display modes up to 4K@60Hz.
> 
> As for the moment HDMI1 output is not supported upstream, the patch
> series targets HDMI0 only.
> 
> Additionally, note that testing any HDMI 2.0 specific modes, e.g.
> 4K@60Hz, requires high TMDS clock ratio and scrambling support [1]. The
> patch is usable but not yet ready to be submitted - I will handle this
> soon.
> 
> Thanks,
> Cristian
> 
> [1] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commits/rk3588-hdmi-bridge-next-20241115
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>

for whole series

Tested-by: FUKAUMI Naoki <naoki@radxa.com>

Diginnos DG-NP09D 8.9inch 1920x1200 display works with your patch!

Name: HSE
EISA ID: ___0001
EDID version: 1.3
EDID extension blocks: 1
Screen size: 120.0 cm x 68.0 cm (54.30 inches, aspect ratio 16/9 = 1.76)
Gamma: 2.2
Digital signal
Max video bandwidth: 160 MHz

	HorizSync 14-91
	VertRefresh 22-80

	# Monitor preferred modeline (59.9 Hz vsync, 74.6 kHz hsync, ratio 
16/10, 40x44 dpi)
	ModeLine "1920x1200" 193.25 1920 2008 2052 2592 1200 1204 1209 1245 
+hsync +vsync

	# Monitor supported modeline (59.9 Hz vsync, 33.7 kHz hsync, 
interlaced, ratio 16/9, 40 dpi)
	ModeLine "1920x1080" 74.18 1920 2008 2052 2200 1080 1084 1094 1125 
+hsync +vsync Interlace

	# Monitor supported CEA modeline (59.9 Hz vsync, 31.5 kHz hsync, ratio 
4/3, 13x17 dpi) (bad ratio)
	ModeLine "640x480" 25.175 640 656 752 800 480 490 492 525 -hsync -vsync

	# Monitor supported CEA modeline (59.9 Hz vsync, 31.5 kHz hsync, ratio 
3/2, 15x17 dpi) (bad ratio)
	ModeLine "720x480" 27 720 736 798 858 480 489 495 525 -hsync -vsync

	# Monitor supported CEA modeline (59.9 Hz vsync, 31.5 kHz hsync, ratio 
3/2, 15x17 dpi) (bad ratio)
	ModeLine "720x480" 27 720 736 798 858 480 489 495 525 -hsync -vsync

	# Monitor supported CEA modeline (60.0 Hz vsync, 45.0 kHz hsync, ratio 
16/9, 27 dpi)
	ModeLine "1280x720" 74.25 1280 1390 1430 1650 720 725 730 750 +hsync +vsync

	# Monitor supported CEA modeline (60.0 Hz vsync, 33.8 kHz hsync, 
interlaced, ratio 16/9, 40 dpi)
	ModeLine "1920x1080" 74.25 1920 2008 2052 2200 1080 1084 1094 1125 
+hsync +vsync Interlace

	# Monitor supported CEA modeline (60.0 Hz vsync, 67.5 kHz hsync, ratio 
16/9, 40 dpi)
	ModeLine "1920x1080" 148.5 1920 2008 2052 2200 1080 1084 1089 1125 
+hsync +vsync

	# Monitor supported CEA modeline (50.0 Hz vsync, 31.2 kHz hsync, ratio 
5/4, 15x21 dpi) (bad ratio)
	ModeLine "720x576" 27 720 732 796 864 576 581 586 625 -hsync -vsync

	# Monitor supported CEA modeline (50.0 Hz vsync, 37.5 kHz hsync, ratio 
16/9, 27 dpi)
	ModeLine "1280x720" 74.25 1280 1720 1760 1980 720 725 730 750 +hsync +vsync

	# Monitor supported CEA modeline (50.0 Hz vsync, 28.1 kHz hsync, 
interlaced, ratio 16/9, 40 dpi)
	ModeLine "1920x1080" 74.25 1920 2448 2492 2640 1080 1084 1094 1125 
+hsync +vsync Interlace

	# Monitor supported CEA modeline (50.0 Hz vsync, 56.2 kHz hsync, ratio 
16/9, 40 dpi)
	ModeLine "1920x1080" 148.5 1920 2448 2492 2640 1080 1084 1089 1125 
+hsync +vsync

	# Monitor supported modeline (85.4 Hz vsync, 44.9 kHz hsync, ratio 
0.97, 9x17 dpi) (bad ratio)
	ModeLine "464x480" 27 464 480 542 602 480 489 495 525 -hsync -vsync

	# Monitor supported modeline (50.0 Hz vsync, 37.5 kHz hsync, ratio 
16/9, 27 dpi)
	ModeLine "1280x720" 74.25 1280 1720 1760 1980 720 725 730 750 +hsync +vsync

	# Monitor supported modeline (50.0 Hz vsync, 28.1 kHz hsync, 
interlaced, ratio 16/9, 40 dpi)
	ModeLine "1920x1080" 74.25 1920 2448 2492 2640 1080 1084 1094 1125 
+hsync +vsync Interlace

	# Monitor supported modeline (59.9 Hz vsync, 31.5 kHz hsync, ratio 3/2, 
15x17 dpi) (bad ratio)
	ModeLine "720x480" 27 720 736 798 858 480 489 495 525 -hsync -vsync

	# Monitor supported modeline (50.0 Hz vsync, 31.2 kHz hsync, ratio 5/4, 
15x21 dpi) (bad ratio)
	ModeLine "720x576" 27 720 732 796 864 576 581 586 625 -hsync -vsync


Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

> ---
> Cristian Ciocaltea (5):
>        dt-bindings: display: vop2: Add optional PLL clock properties
>        drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation
>        drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0
>        arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
>        arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
> 
>   .../bindings/display/rockchip/rockchip-vop2.yaml   |  4 +++
>   arch/arm64/boot/dts/rockchip/rk3588-base.dtsi      |  7 +++--
>   drivers/gpu/drm/rockchip/rockchip_drm_vop2.c       | 36 +++++++++++++++++++++-
>   3 files changed, 44 insertions(+), 3 deletions(-)
> ---
> base-commit: 744cf71b8bdfcdd77aaf58395e068b7457634b2c
> change-id: 20241116-vop2-hdmi0-disp-modes-b39e3619768f