From nobody Fri Nov 22 15:42:22 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 797032F2D; Sat, 16 Nov 2024 18:22:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781371; cv=none; b=WXeXVfJmVqnk9uo9WBMdhsD5/IDxhftITCnG9oAuDD6ycJZnCwtqRB4bzgCu0DeaVmqfs5+0XrXUhmvPDQfh/RrQGlwB0kKiRPhGHDp/KRCvDM1C9fFCzKmBMIs37Requzh7LqHAgbPTalMobnBH68wueTQlfvb0dUcXMV/D8fc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781371; c=relaxed/simple; bh=LM9pPGTp7aEnr4m+OjZM6CvE5/x0hk9Hpk+Ltg9gsoA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c564g7X2DbuulMMMf2/8e+UWOWewtvxc28QsOgHpbC3hh+tEHXMtRdFCHLzk2bNAI51SIcglj0xiu0GDuslt0U2CXLt5z38Qd9YL6rLS7PPJ1tXMEiMrvrZJyAwhG3zcPwBLgbwwtYmR6MUKA6zycg76i97ThqQkOaJNj6Lc9RY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=THAD5DlD; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="THAD5DlD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1731781362; bh=LM9pPGTp7aEnr4m+OjZM6CvE5/x0hk9Hpk+Ltg9gsoA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=THAD5DlDfMEE4ka+eb1K53htNf0/75tr6CJobRdrV0z9lwIZUM3bob9PdEL6rA836 T/BfujG+lglncPzIFhG1tv3kKrrNobc5KTbSHWFyY4K67Ov09Am6iPdNlfgJcWLskd zIHBySIkxCa0ZmeS+Q0aT9CKZ5IAtK9IAsuqaL9jObN1b0vneKMl48a5bQXFpsWHN0 t/VIYkVZrzgHpJ0n046i23OjCtxgHeZPrrrcQjTGyFoQghtSbg2EJHx2iS47DqJfxY V90Y1SiacyMzJ0OupDYxxJ4nxhe3iUV9KX+Bu+NxDbJ1nd+g2Z79qCkEvz9w8JMqTx joqoJZBftbP7A== Received: from localhost (unknown [86.120.21.57]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5121A17E3778; Sat, 16 Nov 2024 19:22:42 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 16 Nov 2024 20:22:32 +0200 Subject: [PATCH 1/5] dt-bindings: display: vop2: Add optional PLL clock properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241116-vop2-hdmi0-disp-modes-v1-1-2bca51db4898@collabora.com> References: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> In-Reply-To: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 On RK3588, HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 video ports 0, 1 and 2. Document the optional PLL clock properties corresponding to the two HDMI PHYs available on the SoC. Signed-off-by: Cristian Ciocaltea Acked-by: Rob Herring (Arm) Tested-by: FUKAUMI Naoki --- Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 4 = ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vo= p2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.= yaml index 2531726af306bd388c00c3c0a1785b2c7367e2bd..46d956e63338e196361483a668f= bf5597ebce24f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -53,6 +53,8 @@ properties: - description: Pixel clock for video port 2. - description: Pixel clock for video port 3. - description: Peripheral(vop grf/dsi) clock. + - description: Alternative pixel clock provided by HDMI0 PHY PLL. + - description: Alternative pixel clock provided by HDMI1 PHY PLL. =20 clock-names: minItems: 5 @@ -64,6 +66,8 @@ properties: - const: dclk_vp2 - const: dclk_vp3 - const: pclk_vop + - const: pll_hdmiphy0 + - const: pll_hdmiphy1 =20 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle --=20 2.47.0 From nobody Fri Nov 22 15:42:22 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEC2A18E050; Sat, 16 Nov 2024 18:22:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781372; cv=none; b=mwiCu5A7b0ZY/AJYOCjsPxUbtiG7V795pFM7si2WS70xx3+i30fJrunYvFnMHYGqJvQugB+7Ho0ckR/9WMudVbgECCz12QqZZoWK++mK12/meKN8IAXPHa2E/I/TquT9ePbEQf+ucZ/GPsBQkYbKubh9ayduPMNCZjYjgTnVovI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781372; c=relaxed/simple; bh=5yLL8RBABIDFFVGZv2n5kbkq6Ay3LOmlFo5JVggJqLg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k7J7I06HFbs9yPPj8+rnGfrSixnQAmmHmaeQUmeak7VzNx+2i7K1dxf6cmBfCZEM/wJ2TObwocQ14DqRptV4Gpo2IHPK6RQs4r1RNY9fVcgBTZbZMDSVfvNPNDOmnafjG/SjsJenTVRXgQFyx/TxAo4DWJieT4aUwXsiEMS4jos= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=obDQbAuV; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="obDQbAuV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1731781363; bh=5yLL8RBABIDFFVGZv2n5kbkq6Ay3LOmlFo5JVggJqLg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=obDQbAuVjSAgWb/fYXKu7UnT53UQHuJZrNXP58OgtW5qfw7iM46xBSBa5hFFjMG/p pb4YEfKB2OJUnLL+YMOOBPAvb+dl3OogjrWUWZUIpQnB+hulCVj7HD4XqDOOPcmpZq kQMMx9prBOzK29MeDzHYdwzc6ByIIWoQN0CX4HtJNk5/d8P11lGToLUFDbIc6/kDT/ HpQTaTiy1U/OcUpq7TOHgJS2e38LPC5xxrUAhrA0PwI81wjF3lEqWlG8xRiPG7YoLU 6fsK+qcmTuNlYavsyiXS/Y5fNCLioW1z7iDHrDPdBUh23GNA4o5K5Dqvvrr1mk4X1J OP9Gz1mG2JW7g== Received: from localhost (unknown [86.120.21.57]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 2A03417E377A; Sat, 16 Nov 2024 19:22:43 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 16 Nov 2024 20:22:33 +0200 Subject: [PATCH 2/5] drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241116-vop2-hdmi0-disp-modes-v1-2-2bca51db4898@collabora.com> References: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> In-Reply-To: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 The if_pixclk_rate variable is not being used outside of the if-block in rk3588_calc_cru_cfg(), hence move the superfluous assignment from the first branch to the inner comment-block. Signed-off-by: Cristian Ciocaltea Tested-by: FUKAUMI Naoki --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 9ad025aa9ab0523c8807b331564c68da10c56c18..3e4c1cfd0bac6fa90f4cab85e27= c2a69b86fc9aa 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1838,8 +1838,8 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_= video_port *vp, int id, K =3D 2; } =20 - if_pixclk_rate =3D (dclk_core_rate << 1) / K; /* + * if_pixclk_rate =3D (dclk_core_rate << 1) / K; * if_dclk_rate =3D dclk_core_rate / K; * *if_pixclk_div =3D dclk_rate / if_pixclk_rate; * *if_dclk_div =3D dclk_rate / if_dclk_rate; --=20 2.47.0 From nobody Fri Nov 22 15:42:22 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 872F11917D0; Sat, 16 Nov 2024 18:22:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781373; cv=none; b=O1Hhz/SuoHo/kItWY1Nj+p854X6CIW2gRDBvnhlskh3B9WuF2R5Msj0F2D0McoHhy4ECxqW6qfhMkMEK+mClolg9VztO0gWXmGZ07OYIQo2FbNh77l6Uy9jTUqogQ7oV3bq63tLrN1mZVcyj63acQmkRx3vZaAyXUOl2OGiTVLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781373; c=relaxed/simple; bh=xZrD/jL4dNv1NcNZfaSbnGqvkzIAEesN0BD0ysPgDCg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RVUV7binDLaM4uYJbX1GAdR93CdNO0gYaFrjdLbCsdV0aHxGF689Etsfy58Tck3/ZnRq+vqgJnBY4znYKTMoZDEvaJHyV3r8WavaIgUz65rZ1v7nSVSxEf7qasLfoYUB3215ts+zE1ZzfwjuFlCjvYHO+m9UWMiDKzqtRpc7Vy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=XDvCv4Fx; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="XDvCv4Fx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1731781364; bh=xZrD/jL4dNv1NcNZfaSbnGqvkzIAEesN0BD0ysPgDCg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XDvCv4FxsDxUwK8lehYWRqyimYPPIFdPKyuLA1UFo6YYcKj3JFihlgC4AIv+yu11F qTKHgZFCMITVpzi+7PXuQGpba7DpRpWkMWDS5lem25UpbPzqP4AKgMIJ/qOAkcYn8k Fe1+FkByqHjtUniC8XoHNbrNL/IAmPBgArhPRWftp1ihd28JXApe9AtQoSV12t530C NWcdHuK23rWfp9EhBrLJ96mRZwcRFRt4hIKeIkqrzRpNAWU2rZ4mvYFOyjj9Q32pQB rg9NYJSnilGbL8naAFW3IfRnFkX063Aulp7vNWD/sVbbs4ukGx8rQuKMDrC18Jftqn aLRf8tArTiExw== Received: from localhost (unknown [86.120.21.57]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id EA52017E377C; Sat, 16 Nov 2024 19:22:43 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 16 Nov 2024 20:22:34 +0200 Subject: [PATCH 3/5] drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241116-vop2-hdmi0-disp-modes-v1-3-2bca51db4898@collabora.com> References: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> In-Reply-To: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 The RK3588 specific implementation is currently quite limited in terms of handling the full range of display modes supported by the connected screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a few of them. Additionally, it doesn't cope well with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of HDMI0 PHY PLL as a more accurate DCLK source to handle all display modes up to 4K@60Hz. Signed-off-by: Cristian Ciocaltea Tested-by: FUKAUMI Naoki --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 34 ++++++++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 3e4c1cfd0bac6fa90f4cab85e27c2a69b86fc9aa..dfe1a50132d596f036430d7db36= 31398d0802972 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -158,6 +158,7 @@ struct vop2_video_port { struct drm_crtc crtc; struct vop2 *vop2; struct clk *dclk; + struct clk *dclk_src; unsigned int id; const struct vop2_video_port_data *data; =20 @@ -212,6 +213,7 @@ struct vop2 { struct clk *hclk; struct clk *aclk; struct clk *pclk; + struct clk *pll_hdmiphy0; =20 /* optional internal rgb encoder */ struct rockchip_rgb *rgb; @@ -220,6 +222,8 @@ struct vop2 { struct vop2_win win[]; }; =20 +#define VOP2_MAX_DCLK_RATE 600000 /* kHz */ + #define vop2_output_if_is_hdmi(x) ((x) =3D=3D ROCKCHIP_VOP2_EP_HDMI0 || \ (x) =3D=3D ROCKCHIP_VOP2_EP_HDMI1) =20 @@ -1103,6 +1107,9 @@ static void vop2_crtc_atomic_disable(struct drm_crtc = *crtc, =20 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); =20 + if (vp->dclk_src) + clk_set_parent(vp->dclk, vp->dclk_src); + clk_disable_unprepare(vp->dclk); =20 vop2->enable_count--; @@ -2192,6 +2199,27 @@ static void vop2_crtc_atomic_enable(struct drm_crtc = *crtc, =20 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); =20 + /* + * Switch to HDMI PHY PLL as DCLK source for display modes up + * to 4K@60Hz, if available, otherwise keep using the system CRU. + */ + if (vop2->pll_hdmiphy0 && mode->crtc_clock <=3D VOP2_MAX_DCLK_RATE) { + drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { + struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); + + if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI0) { + if (!vp->dclk_src) + vp->dclk_src =3D clk_get_parent(vp->dclk); + + ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); + if (ret < 0) + drm_warn(vop2->drm, + "Could not switch to HDMI0 PHY PLL: %d\n", ret); + break; + } + } + } + clk_set_rate(vp->dclk, clock); =20 vop2_post_config(crtc); @@ -3355,6 +3383,12 @@ static int vop2_bind(struct device *dev, struct devi= ce *master, void *data) return PTR_ERR(vop2->pclk); } =20 + vop2->pll_hdmiphy0 =3D devm_clk_get_optional(vop2->dev, "pll_hdmiphy0"); + if (IS_ERR(vop2->pll_hdmiphy0)) { + drm_err(vop2->drm, "failed to get pll_hdmiphy0\n"); + return PTR_ERR(vop2->pll_hdmiphy0); + } + vop2->irq =3D platform_get_irq(pdev, 0); if (vop2->irq < 0) { drm_err(vop2->drm, "cannot find irq for vop2\n"); --=20 2.47.0 From nobody Fri Nov 22 15:42:22 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 581A2198840; Sat, 16 Nov 2024 18:22:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781374; cv=none; b=nAohE30WmRTbvsg/X6pXlwi4pyuvsXXKjUQ/hpursbkhTs7Em0k7jcYV1IaJPVPV7pCGaLQ5Ew+YiSm90gvDhtO8vPVbsD+08/xkXDloYVhyaJ/m5umfuaXOvjOngnTCZH9VY/fxiyGV8j7a36znijlYqF0YFKv7VtJqB5upgkg= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241116-vop2-hdmi0-disp-modes-v1-4-2bca51db4898@collabora.com> References: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> In-Reply-To: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI0 PHY. Signed-off-by: Cristian Ciocaltea Tested-by: FUKAUMI Naoki --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index a337f3fb8377e4a3a200d4d3a3773a237de2bd6e..22462e86f48027ab7c5e270f2fa= 04df7afcc1d24 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -2811,6 +2811,7 @@ hdptxphy_hdmi0: phy@fed60000 { reg =3D <0x0 0xfed60000 0x0 0x2000>; clocks =3D <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; clock-names =3D "ref", "apb"; + #clock-cells =3D <0>; #phy-cells =3D <0>; resets =3D <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, --=20 2.47.0 From nobody Fri Nov 22 15:42:22 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4716F199FA1; Sat, 16 Nov 2024 18:22:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781374; cv=none; b=N1V087XkiPH5F/G7fnH+8vrssFojtrkjqUjqXuqJrno1GzohdFaT8fPKEn93WY7uWLEjg8jGy70wAUYS7T9AuNcGWBpXnKFTJOtWdueZg9Xc6R9Zu7tFUkJHZEvMwTVksR/zZTozUh7vQxqo9cwhQ7SDZSWRNEUcChM4FFa0Gxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781374; c=relaxed/simple; bh=uXHOo9+TzfRpI5IDnIvDAsLN/tG0WK21O4XtRokY5rA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XQ+GBVUbjNz0yFK6FK9OsD9JBEhzp2baV1WXkm4st8X/0NRn5Jg09mzWcBYoqIZN0N+QtSL0FJnyinjZCz3d9tV7BBDsWBQGoXUcT/CT8cE9+9dovyYHFZT9LupAAOs4VCIDSsuWXoLq4a8uGOpc0nqy9Q0jmpMjn1znCZkLE/c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=HbcYmcuw; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="HbcYmcuw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1731781365; bh=uXHOo9+TzfRpI5IDnIvDAsLN/tG0WK21O4XtRokY5rA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HbcYmcuw3KJPwpeen8ioxtv0tN99gDIhC7+J248GqCRUeGsPLf7p0P4AlLJ6NSYoV LDLgkCJU8LE6MGVcKhpTYkLYR0K/GLDlWr7jrpI8mrzM33sOZCkIRyWYgKRlHcmQv9 b9r+vejMaaOTjzqjSkVFQPAC2TV9J3VsKiPGt5I+7DQTGG/55G/mtSYcq7bEYWPlCA 4dxtZf09hiVqQ+4UQUGa3t2jEzqSKOrQ3gdlJ0frXWs4YrA9wnJOndnFKdX6KM1Q/p m+9nUQYn1s9LzFgM+1AHuyZ+E4BrWgoON2gB1qVGvLa2IbA1ml+o9Smr87sgSt0BKY fndRSwruUh1HA== Received: from localhost (unknown [86.120.21.57]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9146917E377E; Sat, 16 Nov 2024 19:22:45 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 16 Nov 2024 20:22:36 +0200 Subject: [PATCH 5/5] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241116-vop2-hdmi0-disp-modes-v1-5-2bca51db4898@collabora.com> References: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> In-Reply-To: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2. For now only HDMI0 output is supported, hence add the related PLL clock. Signed-off-by: Cristian Ciocaltea Tested-by: FUKAUMI Naoki --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 22462e86f48027ab7c5e270f2fa04df7afcc1d24..d07be2a81f28b4cbfe314992c66= 2d8cfb3d3d344 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1262,14 +1262,16 @@ vop: vop@fdd90000 { <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; + <&cru PCLK_VOP_ROOT>, + <&hdptxphy_hdmi0>; clock-names =3D "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", - "pclk_vop"; + "pclk_vop", + "pll_hdmiphy0"; iommus =3D <&vop_mmu>; power-domains =3D <&power RK3588_PD_VOP>; rockchip,grf =3D <&sys_grf>; --=20 2.47.0