Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The SDHC1
and SDHC2 of QCS615 are derived from SM6115. Include the relevant
binding documents accordingly. Additionally, configure SDHC1-related
and SDHC2-related opp, power, and interconnect settings in the device
tree.
Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
1 file changed, 198 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 590beb37f441..37c6ab217c96 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -399,6 +399,65 @@ qfprom: efuse@780000 {
#size-cells = <1>;
};
+ sdhc_1: mmc@7c4000 {
+ compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x007c4000 0x0 0x1000>,
+ <0x0 0x007c5000 0x0 0x1000>;
+ reg-names = "hc",
+ "cqhci";
+
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo",
+ "ice";
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+ iommus = <&apps_smmu 0x02c0 0x0>;
+ interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ bus-width = <8>;
+ qcom,dll-config = <0x000f642c>;
+ qcom,ddr-config = <0x80040868>;
+ supports-cqe;
+ dma-coherent;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -494,6 +553,145 @@ qup_uart0_rx: qup-uart0-rx-state {
pins = "gpio17";
function = "qup0";
};
+
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_state_on: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc2_state_off: sdc2-off-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+ };
+
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>;
+ reg-names = "hc";
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ iommus = <&apps_smmu 0x02a0 0x0>;
+ resets = <&gcc GCC_SDCC2_BCR>;
+ interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ bus-width = <4>;
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ dma-coherent;
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
dc_noc: interconnect@9160000 {
--
2.34.1On Wed, Nov 06, 2024 at 03:23:42PM +0800, Yuanjie Yang wrote: > Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The SDHC1 > and SDHC2 of QCS615 are derived from SM6115. Include the relevant > binding documents accordingly. Which binding documents? > Additionally, configure SDHC1-related > and SDHC2-related opp, power, and interconnect settings in the device > tree. > > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ > 1 file changed, 198 insertions(+) > -- With best wishes Dmitry
On Wed, Nov 06, 2024 at 09:36:56AM +0200, Dmitry Baryshkov wrote: > On Wed, Nov 06, 2024 at 03:23:42PM +0800, Yuanjie Yang wrote: > > Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The SDHC1 > > and SDHC2 of QCS615 are derived from SM6115. Include the relevant > > binding documents accordingly. > > Which binding documents? Thanks, the binding documents is sdhci-msm.yaml. I have modified this yaml patch in patch v1, and this yaml patch is applied, so I remove this yaml patch in patch v2. link:https://lore.kernel.org/all/CAPDyKFr-Gzd3Mzn+vN6DXO9C4Xrvpv4z5V2G_VRTzOa=89Fd3w@mail.gmail.com/ > > Additionally, configure SDHC1-related > > and SDHC2-related opp, power, and interconnect settings in the device > > tree. > > > > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ > > 1 file changed, 198 insertions(+) > > > > -- > With best wishes > Dmitry Thanks, Yuanjie
On 6 November 2024 07:56:57 GMT, Yuanjie Yang <quic_yuanjiey@quicinc.com> wrote: >On Wed, Nov 06, 2024 at 09:36:56AM +0200, Dmitry Baryshkov wrote: >> On Wed, Nov 06, 2024 at 03:23:42PM +0800, Yuanjie Yang wrote: >> > Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The SDHC1 >> > and SDHC2 of QCS615 are derived from SM6115. Include the relevant >> > binding documents accordingly. >> >> Which binding documents? >Thanks, the binding documents is sdhci-msm.yaml. >I have modified this yaml patch in patch v1, and this yaml patch is >applied, so I remove this yaml patch in patch v2. >link:https://lore.kernel.org/all/CAPDyKFr-Gzd3Mzn+vN6DXO9C4Xrvpv4z5V2G_VRTzOa=89Fd3w@mail.gmail.com/ The question is why do you mention bindings in the DTSI commit message? Please don't just C&P your texts. > >> > Additionally, configure SDHC1-related >> > and SDHC2-related opp, power, and interconnect settings in the device >> > tree. >> > >> > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> >> > --- >> > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ >> > 1 file changed, 198 insertions(+) >> > >> >> -- >> With best wishes >> Dmitry > >Thanks, >Yuanjie
On Wed, Nov 06, 2024 at 09:10:57AM +0000, Dmitry Baryshkov wrote: > On 6 November 2024 07:56:57 GMT, Yuanjie Yang <quic_yuanjiey@quicinc.com> wrote: > >On Wed, Nov 06, 2024 at 09:36:56AM +0200, Dmitry Baryshkov wrote: > >> On Wed, Nov 06, 2024 at 03:23:42PM +0800, Yuanjie Yang wrote: > >> > Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The SDHC1 > >> > and SDHC2 of QCS615 are derived from SM6115. Include the relevant > >> > binding documents accordingly. > >> > >> Which binding documents? > >Thanks, the binding documents is sdhci-msm.yaml. > >I have modified this yaml patch in patch v1, and this yaml patch is > >applied, so I remove this yaml patch in patch v2. > >link:https://lore.kernel.org/all/CAPDyKFr-Gzd3Mzn+vN6DXO9C4Xrvpv4z5V2G_VRTzOa=89Fd3w@mail.gmail.com/ > > The question is why do you mention bindings in the DTSI commit message? Please don't just C&P your texts. Thanks, I will adjust commit message in next version. I will optimize my language expression again. > > > >> > Additionally, configure SDHC1-related > >> > and SDHC2-related opp, power, and interconnect settings in the device > >> > tree. > >> > > >> > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> > >> > --- > >> > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ > >> > 1 file changed, 198 insertions(+) > >> > > >> > >> -- > >> With best wishes > >> Dmitry > > > >Thanks, > >Yuanjie > Thanks, Yuanjie
© 2016 - 2024 Red Hat, Inc.