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charset="utf-8" Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The SDHC1 and SDHC2 of QCS615 are derived from SM6115. Include the relevant binding documents accordingly. Additionally, configure SDHC1-related and SDHC2-related opp, power, and interconnect settings in the device tree. Signed-off-by: Yuanjie Yang --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 590beb37f441..37c6ab217c96 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -399,6 +399,65 @@ qfprom: efuse@780000 { #size-cells =3D <1>; }; =20 + sdhc_1: mmc@7c4000 { + compatible =3D "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x007c4000 0x0 0x1000>, + <0x0 0x007c5000 0x0 0x1000>; + reg-names =3D "hc", + "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names =3D "iface", + "core", + "xo", + "ice"; + + resets =3D <&gcc GCC_SDCC1_BCR>; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc1_opp_table>; + iommus =3D <&apps_smmu 0x02c0 0x0>; + interconnects =3D <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "sdhc-ddr", + "cpu-sdhc"; + + bus-width =3D <8>; + qcom,dll-config =3D <0x000f642c>; + qcom,ddr-config =3D <0x80040868>; + supports-cqe; + dma-coherent; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status =3D "disabled"; + + sdhc1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-384000000 { + opp-hz =3D /bits/ 64 <384000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + qupv3_id_0: geniqup@8c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0x0 0x008c0000 0x0 0x6000>; @@ -494,6 +553,145 @@ qup_uart0_rx: qup-uart0-rx-state { pins =3D "gpio17"; function =3D "qup0"; }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <16>; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + bias-pull-up; + drive-strength =3D <10>; + }; + + data-pins { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + bias-pull-up; + drive-strength =3D <2>; + }; + + data-pins { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <16>; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <10>; + }; + + data-pins { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <2>; + }; + + data-pins { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + }; + }; + + sdhc_2: mmc@8804000 { + compatible =3D "qcom,qcs615-sdhci","qcom,sdhci-msm-v5"; + reg =3D <0x0 0x08804000 0x0 0x1000>; + reg-names =3D "hc"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "core", + "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + iommus =3D <&apps_smmu 0x02a0 0x0>; + resets =3D <&gcc GCC_SDCC2_BCR>; + interconnects =3D <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "sdhc-ddr", + "cpu-sdhc"; + + bus-width =3D <4>; + qcom,dll-config =3D <0x0007642c>; + qcom,ddr-config =3D <0x80040868>; + dma-coherent; + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; }; =20 dc_noc: interconnect@9160000 { --=20 2.34.1