Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
integration in the TI k3-j721s2.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
---
 .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 45 ++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
index 8a1861ca960c48853b2ceef414f588cc343b49b2..d3a28d758ae78a69afbf26b7317a1c55c6b0a517 100644
--- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
@@ -18,6 +18,11 @@ properties:
               - ti,am62-gpu
           - const: img,img-axe-1-16m
           - const: img,img-rogue
+      - items:
+          - enum:
+              - ti,j721s2-gpu
+          - const: img,img-bxs-4-64
+          - const: img,img-rogue
 
       # This legacy combination of compatible strings was introduced early on before the more
       # specific GPU identifiers were used. Keep it around here for compatibility, but never use
@@ -89,6 +94,22 @@ allOf:
         power-domain-names:
           items:
             - const: a
+  # Cores with two power domains
+  - if:
+      properties:
+        compatible:
+          contains:
+            anyOf:
+              - const: img,img-bxs-4-64
+    then:
+      properties:
+        power-domains:
+          minItems: 2
+          maxItems: 2
+        power-domain-names:
+          items:
+            - const: a
+            - const: b
   # Vendor integrations using a single clock domain
   - if:
       properties:
@@ -96,6 +117,7 @@ allOf:
           contains:
             anyOf:
               - const: ti,am62-gpu
+              - const: ti,j721s2-gpu
     then:
       properties:
         clocks:
@@ -120,3 +142,26 @@ examples:
         power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
         power-domain-names = "a";
     };
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+    / {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <3>;
+
+        gpu@4e20000000 {
+            compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue";
+            reg = /bits/ 64 <0x4e20000000 0x80000>;
+            clocks = <&k3_clks 130 1>;
+            clock-names = "core";
+            interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+            power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>,
+                            <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>;
+            power-domain-names = "a", "b";
+            dma-coherent;
+        };
+    };

-- 
2.47.0

On Tue, Nov 05, 2024 at 03:58:14PM +0000, Matt Coster wrote:
> +    / {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        interrupt-controller;
> +        #interrupt-cells = <3>;
> +
> +        gpu@4e20000000 {
> +            compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue";
> +            reg = /bits/ 64 <0x4e20000000 0x80000>;

Can you format this normally please? Drop the #address/size-cells down
to 1 if you're against having 0x0s.

Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>


> +            clocks = <&k3_clks 130 1>;
> +            clock-names = "core";
> +            interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> +            power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>,
> +                            <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>;
> +            power-domain-names = "a", "b";
> +            dma-coherent;
> +        };
> +    };
> 
> -- 
> 2.47.0
> 

On 05/11/2024 18:03, Conor Dooley wrote:
> On Tue, Nov 05, 2024 at 03:58:14PM +0000, Matt Coster wrote:
>> +    / {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +        interrupt-controller;
>> +        #interrupt-cells = <3>;
>> +
>> +        gpu@4e20000000 {
>> +            compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue";
>> +            reg = /bits/ 64 <0x4e20000000 0x80000>;
> 
> Can you format this normally please? Drop the #address/size-cells down
> to 1 if you're against having 0x0s.

Sure. I thought /bits/ was the "new" way of doing things, but I'm not
really bothered either way.

Cheers,
Matt

> Otherwise,
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
> 
>> +            clocks = <&k3_clks 130 1>;
>> +            clock-names = "core";
>> +            interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>> +            power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>,
>> +                            <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>;
>> +            power-domain-names = "a", "b";
>> +            dma-coherent;
>> +        };
>> +    };
>>
>> -- 
>> 2.47.0
>>

-- 
Matt Coster
E: matt.coster@imgtec.com

On Wed, Nov 06, 2024 at 10:18:10AM +0000, Matt Coster wrote:
> On 05/11/2024 18:03, Conor Dooley wrote:
> > On Tue, Nov 05, 2024 at 03:58:14PM +0000, Matt Coster wrote:
> >> +    / {
> >> +        #address-cells = <2>;
> >> +        #size-cells = <2>;
> >> +        interrupt-controller;
> >> +        #interrupt-cells = <3>;
> >> +
> >> +        gpu@4e20000000 {
> >> +            compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue";
> >> +            reg = /bits/ 64 <0x4e2000 0000 0x80000>;
> > 
> > Can you format this normally please? Drop the #address/size-cells down
> > to 1 if you're against having 0x0s.
> 
> Sure. I thought /bits/ was the "new" way of doing things, but I'm not
> really bothered either way.

Maybe in other cases, I've never seen it for reg. The dts coding style
examples even have 0x0s in them. For other properties, sure this might
be the "new" way of doing it but not for reg, probably in part because
it makes it difficult to see if the number matches the number of cells
in #address/size-cells.