From nobody Sun Nov 24 14:34:02 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FE441684AC; Tue, 5 Nov 2024 15:59:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822390; cv=none; b=bIQs4d4vKInYi8/SYSCPRZmAAlmZC7pTIDjAZvWkYga52i6Gk4Dn7zgdaQ9U6HqqFRD/3LnJY/kw9X8xrPFqWyhEdB0wxTSoRInVgk0q79poIn9fc79JR4TtI3fh3hgYavZlea4ziAgkg07svzaPsbSetjZFFksWr0oPtttqYQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822390; c=relaxed/simple; bh=KmZHQpu6U9dqLtldHbo5s6lUvD4SI5/Z7CglFP7B090=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=U+Xd5x65dPvJCvRQ6ZI1ahZaVxMIqMoI0DDHO8SAPegIWRiGYqZcvJikjhEv/VOyGgm7icZVphj+3Yg7AFCIKeenKgY9HB7N/Ae63aTnSVoWKPUBLxM+GdH6lfyGEzKUqK6KIQm672hLWBe558ZwmnxSMq6Z9qYdiIu4zd10uxI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=CtPQKZRh; arc=none smtp.client-ip=185.132.180.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="CtPQKZRh" Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A5DjjHX028612; Tue, 5 Nov 2024 15:58:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=A dcimgP6TdRefkK6ZXHyBiKyLfJbpiMR1HIyssxuJK8=; b=CtPQKZRh/rm6+lmI+ QOzTIVzI/yKoQA8GbiDVsOXOFOXICBaD/+txb3tPwcSBRXnniGe9qB1+BdGD3ue2 J+dFiN2glIGHa6vjvLXPU3VMo03zpDkIoSa9uKGIvN+6dQ/MTU4MqMUIf5DZHRPw C4ffIiaGDY3Yty4s5Du0d8UiKIKJg7hxbA2emrzrdtkkiNSk2yXAdj3/zMVBCTyH TDkdyiqKaiu+kjMN9yUjc0fvX/y0KAaEZExZJl39yXRltwYcIne2MAOgOf1xypzR h5XYZ3eVwuVRhhPSWI6jEHeiYtUydPeTzKyDEGlUny4GYemaHhoRcz8fjpCGD9Tg HNeWw== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 42nd212jtx-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 05 Nov 2024 15:58:30 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 5 Nov 2024 15:58:29 +0000 From: Matt Coster Date: Tue, 5 Nov 2024 15:58:14 +0000 Subject: [PATCH 08/21] dt-bindings: gpu: img: Add BXS-4-64 devicetree bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241105-sets-bxs-4-64-patch-v1-v1-8-4ed30e865892@imgtec.com> References: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> In-Reply-To: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2886; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=KmZHQpu6U9dqLtldHbo5s6lUvD4SI5/Z7CglFP7B090=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRrOcwta1w6bWFniZyN/471ddGl7H7xJsWvbmnZP7zT/ UBD58PljlIWBjEOBlkxRZYdKyxXqP1R05K48asYZg4rE8gQBi5OAZjI9niG/6mzF09SFyjYtVe5 ZOYF98RCjpUNoUohDa+lHQy/m10pr2JkeG5Qz6094eje35HOT63mRc2wOG7hPqueOSotv2Lefn8 BZgA= X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=Q9aA4J2a c=1 sm=1 tr=0 ts=672a40a6 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=r_1tXGB3AAAA:8 a=fBGHU3NjAIazuI7ybSQA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: fFSOzA_pDUezOPUZAJmOYLhlSiHupNJv X-Proofpoint-ORIG-GUID: fFSOzA_pDUezOPUZAJmOYLhlSiHupNJv Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock integration in the TI k3-j721s2. Signed-off-by: Matt Coster Reviewed-by: Conor Dooley --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 45 ++++++++++++++++++= ++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 8a1861ca960c48853b2ceef414f588cc343b49b2..d3a28d758ae78a69afbf26b7317= a1c55c6b0a517 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -18,6 +18,11 @@ properties: - ti,am62-gpu - const: img,img-axe-1-16m - const: img,img-rogue + - items: + - enum: + - ti,j721s2-gpu + - const: img,img-bxs-4-64 + - const: img,img-rogue =20 # This legacy combination of compatible strings was introduced early= on before the more # specific GPU identifiers were used. Keep it around here for compat= ibility, but never use @@ -89,6 +94,22 @@ allOf: power-domain-names: items: - const: a + # Cores with two power domains + - if: + properties: + compatible: + contains: + anyOf: + - const: img,img-bxs-4-64 + then: + properties: + power-domains: + minItems: 2 + maxItems: 2 + power-domain-names: + items: + - const: a + - const: b # Vendor integrations using a single clock domain - if: properties: @@ -96,6 +117,7 @@ allOf: contains: anyOf: - const: ti,am62-gpu + - const: ti,j721s2-gpu then: properties: clocks: @@ -120,3 +142,26 @@ examples: power-domains =3D <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; power-domain-names =3D "a"; }; + - | + #include + #include + #include + + / { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <3>; + + gpu@4e20000000 { + compatible =3D "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-r= ogue"; + reg =3D /bits/ 64 <0x4e20000000 0x80000>; + clocks =3D <&k3_clks 130 1>; + clock-names =3D "core"; + interrupts =3D ; + power-domains =3D <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + power-domain-names =3D "a", "b"; + dma-coherent; + }; + }; --=20 2.47.0