Add support for video, camera, display0 and display1 clock controllers
on SA8775P. The dispcc1 will be enabled based on board requirements.
Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 57 +++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index e8dbc8d820a64f45c62edebca7ce4583a5c716e0..e56a725128e5ec228133a1b008ac2114a4682bef 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3254,6 +3254,47 @@ llcc: system-cache-controller@9200000 {
interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
};
+ videocc: clock-controller@abf0000 {
+ compatible = "qcom,sa8775p-videocc";
+ reg = <0x0 0x0abf0000 0x0 0x10000>;
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,sa8775p-camcc";
+ reg = <0x0 0x0ade0000 0x0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc0: clock-controller@af00000 {
+ compatible = "qcom,sa8775p-dispcc0";
+ reg = <0x0 0x0af00000 0x0 0x20000>;
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <0>, <0>, <0>, <0>,
+ <0>, <0>, <0>, <0>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
@@ -3876,6 +3917,22 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
+ dispcc1: clock-controller@22100000 {
+ compatible = "qcom,sa8775p-dispcc1";
+ reg = <0x0 0x22100000 0x0 0x20000>;
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <0>, <0>, <0>, <0>,
+ <0>, <0>, <0>, <0>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ status = "disabled";
+ };
+
ethernet1: ethernet@23000000 {
compatible = "qcom,sa8775p-ethqos";
reg = <0x0 0x23000000 0x0 0x10000>,
--
2.45.2On 25.10.2024 10:52 AM, Taniya Das wrote: > Add support for video, camera, display0 and display1 clock controllers > on SA8775P. The dispcc1 will be enabled based on board requirements. > > Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
On 25.10.2024 8:42 PM, Konrad Dybcio wrote: > On 25.10.2024 10:52 AM, Taniya Das wrote: >> Add support for video, camera, display0 and display1 clock controllers >> on SA8775P. The dispcc1 will be enabled based on board requirements. Actually, why would that be? CCF should park it gracefully with unused cleanup Konrad >> >> Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > > Konrad
On 10/26/2024 12:12 AM, Konrad Dybcio wrote: > On 25.10.2024 8:42 PM, Konrad Dybcio wrote: >> On 25.10.2024 10:52 AM, Taniya Das wrote: >>> Add support for video, camera, display0 and display1 clock controllers >>> on SA8775P. The dispcc1 will be enabled based on board requirements. > > Actually, why would that be? CCF should park it gracefully with > unused cleanup > Yes, CCF should take care to cleanup. But I am of an opinion that as we are aware that this platform do not require the dispcc1 so we could avoid the clock driver initialization and help in boot KPI. > Konrad > >>> >>> Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>> --- >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> >> >> Konrad -- Thanks & Regards, Taniya Das.
On Tue, Dec 03, 2024 at 10:04:13AM +0530, Taniya Das wrote: > > > On 10/26/2024 12:12 AM, Konrad Dybcio wrote: > > On 25.10.2024 8:42 PM, Konrad Dybcio wrote: > > > On 25.10.2024 10:52 AM, Taniya Das wrote: > > > > Add support for video, camera, display0 and display1 clock controllers > > > > on SA8775P. The dispcc1 will be enabled based on board requirements. > > > > Actually, why would that be? CCF should park it gracefully with > > unused cleanup > > > > Yes, CCF should take care to cleanup. But I am of an opinion that as we are > aware that this platform do not require the dispcc1 so we could avoid the > clock driver initialization and help in boot KPI. > Does that imply that we're guaranteed that the bootloader will never configure any clocks in dispcc1 that needs to be gracefully parked from the OS? Is this guaranteed to be the case for all QCS9100 boards? IMHO we should default to correctness, and then make product-specific boot time optimizations from that starting point. Regards, Bjorn > > Konrad > > > > > > > > > > Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com> > > > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > > > > --- > > > > > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > > > > > > Konrad > > -- > Thanks & Regards, > Taniya Das.
On 12/3/2024 9:02 PM, Bjorn Andersson wrote: > On Tue, Dec 03, 2024 at 10:04:13AM +0530, Taniya Das wrote: >> >> >> On 10/26/2024 12:12 AM, Konrad Dybcio wrote: >>> On 25.10.2024 8:42 PM, Konrad Dybcio wrote: >>>> On 25.10.2024 10:52 AM, Taniya Das wrote: >>>>> Add support for video, camera, display0 and display1 clock controllers >>>>> on SA8775P. The dispcc1 will be enabled based on board requirements. >>> >>> Actually, why would that be? CCF should park it gracefully with >>> unused cleanup >>> >> >> Yes, CCF should take care to cleanup. But I am of an opinion that as we are >> aware that this platform do not require the dispcc1 so we could avoid the >> clock driver initialization and help in boot KPI. >> > > Does that imply that we're guaranteed that the bootloader will never > configure any clocks in dispcc1 that needs to be gracefully parked from > the OS? Is this guaranteed to be the case for all QCS9100 boards? > Yes, bootloader will never use DISPCC1. > IMHO we should default to correctness, and then make product-specific > boot time optimizations from that starting point. > As I was sure it will not be used on this board, so I left it disabled. > Regards, > Bjorn > >>> Konrad >>> >>>>> >>>>> Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>>>> --- >>>> >>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> >>>> >>>> Konrad >> >> -- >> Thanks & Regards, >> Taniya Das. -- Thanks & Regards, Taniya Das.
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