From nobody Mon Nov 25 20:52:20 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28F0E1D4323; Fri, 25 Oct 2024 08:53:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729846406; cv=none; b=APMIxxy136QtpjT+wzuQvGc0Mxr1vWOc6fUSVhmi+SSEPIUHSOb4PhErwtR+0rWJWYfa9FGLJK+4aCqYOFdGWzkkt+Nn0sCQZBg95sJSkjAqsld38J/oREr5sU63YQdVXs8+X5nHid7lGlPdzT6yGQKemg8PU0FLMv62fV/vcaQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729846406; c=relaxed/simple; bh=J7TqI8bF6c0dVOvYEMiTjVbj+BuCrhlUGy+UNM4Ic48=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=B6YEOXn0+GkF7cWJK+S53pIFFhsNdun/gGY4z+3CpHp9ZTJXYztXe5GirUbfJvtyXSxrf8qJJQBnJXNbun0+K/vYdeKGLyOBnKyQv0VVzzSO9KBG6ZjwiIazDgDmiSK8zdfGaMEDFF6rblSmTSD9rYiX1KdnpdCUIbc03srtZwo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=f6Cp1j9e; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="f6Cp1j9e" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49ONeoue032158; Fri, 25 Oct 2024 08:53:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zwt5AKDXoZAeFZ3EBfDIUfj2UFrPIczBTEA5Y6L/mtU=; b=f6Cp1j9eOxKzjpBg 6XRYKQifIsYu9nREROTTkqMf1QdK+2sJmJTJtcm0BM38OPUBg9sQe/8TYaJeUevP lTZmoI3q1n+CwMQin4GNWIW/L8cjD4pV/6MjDoBAvTuPU2bqnhbYZB3+NlBbxxBp eN1AOYsU9k8PWX86xwxN7y3jPqrqqngISTGspBXE36oWqwA/6YpL2wsiBaq1A3rg lJ2t3XJsmLdlZdoEoe18nGBd8JragXpCwHKjkboTcN7ribh2EyvJsNL7/h3MZwNm pRno1ESA3JJhtHwshy2BPGLmaOPD9WFqT+WReBUKH11n2lt6Hy3inNIrzIqgEdYd sD8vzw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em3w0d1w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 08:53:20 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49P8rJdC004894 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 08:53:19 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 25 Oct 2024 01:53:14 -0700 From: Taniya Das Date: Fri, 25 Oct 2024 14:22:54 +0530 Subject: [PATCH v6 2/2] arm64: dts: qcom: sa8775p: Add support for clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241025-sa8775p-mm-v4-resend-patches-v6-2-329a2cac09ae@quicinc.com> References: <20241025-sa8775p-mm-v4-resend-patches-v6-0-329a2cac09ae@quicinc.com> In-Reply-To: <20241025-sa8775p-mm-v4-resend-patches-v6-0-329a2cac09ae@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , , Bartosz Golaszewski CC: , , , , Ajit Pandey , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: k4BS01a4a5fesVmdYLYrZvSqU9TCNyfS X-Proofpoint-ORIG-GUID: k4BS01a4a5fesVmdYLYrZvSqU9TCNyfS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=950 priorityscore=1501 mlxscore=0 suspectscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250068 Add support for video, camera, display0 and display1 clock controllers on SA8775P. The dispcc1 will be enabled based on board requirements. Reviewed-by: Jagadeesh Kona Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 57 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index e8dbc8d820a64f45c62edebca7ce4583a5c716e0..e56a725128e5ec228133a1b008a= c2114a4682bef 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3254,6 +3254,47 @@ llcc: system-cache-controller@9200000 { interrupts =3D ; }; =20 + videocc: clock-controller@abf0000 { + compatible =3D "qcom,sa8775p-videocc"; + reg =3D <0x0 0x0abf0000 0x0 0x10000>; + clocks =3D <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@ade0000 { + compatible =3D "qcom,sa8775p-camcc"; + reg =3D <0x0 0x0ade0000 0x0 0x20000>; + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc0: clock-controller@af00000 { + compatible =3D "qcom,sa8775p-dispcc0"; + reg =3D <0x0 0x0af00000 0x0 0x20000>; + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sa8775p-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x30000>, @@ -3876,6 +3917,22 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; =20 + dispcc1: clock-controller@22100000 { + compatible =3D "qcom,sa8775p-dispcc1"; + reg =3D <0x0 0x22100000 0x0 0x20000>; + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + status =3D "disabled"; + }; + ethernet1: ethernet@23000000 { compatible =3D "qcom,sa8775p-ethqos"; reg =3D <0x0 0x23000000 0x0 0x10000>, --=20 2.45.2