iommu/arm-smmu-v3: bypass streamid zero on i.MX95

[PATCH RFC 0/2] iommu/arm-smmu-v3: bypass streamid zero on i.MX95

Posted by Peng Fan (OSS) 1 month, 1 week ago

i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent memory to
memory operations. However TBU is in the path between eDMA3 and ACP,
need to bypass the default SID 0 to make eDMA3 work properly.

I was also thinking to introduce "bypass-sids = <0xA 0xB 0xC ...>" to
make this reusable for others, but not sure. I could switch to
"bypass-sids" if you prefer.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Peng Fan (2):
      dt-bindings: iommu: arm,smmu-v3: introduce nxp,imx95-bypass-sid-zero
      iommu/arm-smmu-v3: Bypass SID0 for NXP i.MX95

 .../devicetree/bindings/iommu/arm,smmu-v3.yaml        |  4 ++++
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c           | 19 ++++++++++++++++---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h           |  1 +
 3 files changed, 21 insertions(+), 3 deletions(-)
---
base-commit: d61a00525464bfc5fe92c6ad713350988e492b88
change-id: 20241014-smmuv3-120b24bc4659

Best regards,
-- 
Peng Fan <peng.fan@nxp.com>

Re: [PATCH RFC 0/2] iommu/arm-smmu-v3: bypass streamid zero on i.MX95

Posted by Robin Murphy 1 month, 1 week ago

On 2024-10-15 4:14 am, Peng Fan (OSS) wrote:
> i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent memory to
> memory operations. However TBU is in the path between eDMA3 and ACP,
> need to bypass the default SID 0 to make eDMA3 work properly.

I'm confused, why not just describe that the device owns this StreamID 
in the DT the normal way, i.e, "iommus = <&smmu 0>;"?

Thanks,
Robin.

> I was also thinking to introduce "bypass-sids = <0xA 0xB 0xC ...>" to
> make this reusable for others, but not sure. I could switch to
> "bypass-sids" if you prefer.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> Peng Fan (2):
>        dt-bindings: iommu: arm,smmu-v3: introduce nxp,imx95-bypass-sid-zero
>        iommu/arm-smmu-v3: Bypass SID0 for NXP i.MX95
> 
>   .../devicetree/bindings/iommu/arm,smmu-v3.yaml        |  4 ++++
>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c           | 19 ++++++++++++++++---
>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h           |  1 +
>   3 files changed, 21 insertions(+), 3 deletions(-)
> ---
> base-commit: d61a00525464bfc5fe92c6ad713350988e492b88
> change-id: 20241014-smmuv3-120b24bc4659
> 
> Best regards,

Re: [PATCH RFC 0/2] iommu/arm-smmu-v3: bypass streamid zero on i.MX95

Posted by Pranjal Shrivastava 1 month, 1 week ago

Hi Peng,

On Tue, Oct 15, 2024 at 11:14:41AM +0800, Peng Fan (OSS) wrote:
> i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent memory to
> memory operations. However TBU is in the path between eDMA3 and ACP,
> need to bypass the default SID 0 to make eDMA3 work properly.
> 
> I was also thinking to introduce "bypass-sids = <0xA 0xB 0xC ...>" to
> make this reusable for others, but not sure. I could switch to
> "bypass-sids" if you prefer.

Any reason why you can't use the sysfs to change the iommu domain type?
i.e. by using the /sys/kernel/iommu_groups/<iommu_group_number>/type
AFAIK, the arm-smmu-v3 driver allocates one iommu_group per device.

> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> Peng Fan (2):
>       dt-bindings: iommu: arm,smmu-v3: introduce nxp,imx95-bypass-sid-zero
>       iommu/arm-smmu-v3: Bypass SID0 for NXP i.MX95
> 
>  .../devicetree/bindings/iommu/arm,smmu-v3.yaml        |  4 ++++
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c           | 19 ++++++++++++++++---
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h           |  1 +
>  3 files changed, 21 insertions(+), 3 deletions(-)
> ---
> base-commit: d61a00525464bfc5fe92c6ad713350988e492b88
> change-id: 20241014-smmuv3-120b24bc4659
> 
> Best regards,
> -- 
> Peng Fan <peng.fan@nxp.com>
> 
> 

Thanks,
Pranjal