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However TBU is in the path between eDMA3 and ACP, need to bypass the default SID 0 to make eDMA3 work properly. Introduce the property "nxp,imx95-bypass-sid-zero" for bypassing SID 0. Signed-off-by: Peng Fan --- Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Doc= umentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9f6449238578f20288966af35cab3..88ab908154e31aabf98f3bbe4df= 348956f49d5e1 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -69,6 +69,10 @@ properties: register access with page 0 offsets. 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However TBU is in the path between eDMA3 and ACP, need to bypass the default SID 0 to make eDMA3 work properly. Signed-off-by: Peng Fan --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 19 ++++++++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 737c5b88235510e3ddb91a28cecbdcdc14854b32..3db7b3e2ac94e16130fc0356f79= 54ffa1a9dfb33 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -80,6 +80,7 @@ DEFINE_MUTEX(arm_smmu_asid_lock); static struct arm_smmu_option_prop arm_smmu_options[] =3D { { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"}, + { ARM_SMMU_OPT_IMX95_BYPASS_SID0, "nxp,imx95-bypass-sid-zero"}, { 0, NULL}, }; =20 @@ -4465,7 +4466,7 @@ static void __iomem *arm_smmu_ioremap(struct device *= dev, resource_size_t start, return devm_ioremap_resource(dev, &res); } =20 -static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) +static void arm_smmu_install_bypass_ste(struct arm_smmu_device *smmu) { struct list_head rmr_list; struct iommu_resv_region *e; @@ -4496,6 +4497,18 @@ static void arm_smmu_rmr_install_bypass_ste(struct a= rm_smmu_device *smmu) } =20 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); + + if (smmu->options & ARM_SMMU_OPT_IMX95_BYPASS_SID0) { + int ret =3D arm_smmu_init_sid_strtab(smmu, 0); + + if (ret) { + dev_err(smmu->dev, "i.MX95 SID0 bypass failed\n"); + return; + } + + arm_smmu_make_bypass_ste(smmu, + arm_smmu_get_step_for_sid(smmu, 0)); + } } =20 static void arm_smmu_impl_remove(void *data) @@ -4614,8 +4627,8 @@ static int arm_smmu_device_probe(struct platform_devi= ce *pdev) /* Record our private device structure */ platform_set_drvdata(pdev, smmu); =20 - /* Check for RMRs and install bypass STEs if any */ - arm_smmu_rmr_install_bypass_ste(smmu); + /* Install bypass STEs if any */ + arm_smmu_install_bypass_ste(smmu); =20 /* Reset the device */ ret =3D arm_smmu_device_reset(smmu); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 1e9952ca989f87957197f4d4b400f9d74bb685ac..06481b923284776e7dc4f3301e5= cbe8ab7869a9c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -733,6 +733,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_MSIPOLL (1 << 2) #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) +#define ARM_SMMU_OPT_IMX95_BYPASS_SID0 (1 << 5) u32 options; =20 struct arm_smmu_cmdq cmdq; --=20 2.37.1