Add support for USB controllers on QCS8300. The second
controller is only High Speed capable.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 165 ++++++++++++++++++++++++++
1 file changed, 165 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 2c35f96c3f28..701b834e9b58 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -1363,6 +1363,171 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
qcom,remote-pid = <5>;
};
};
+
+ usb_1_hsphy: phy@8904000 {
+ compatible = "qcom,qcs8300-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0x0 0x8904000 0x0 0x400>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy: phy@8906000 {
+ compatible = "qcom,qcs8300-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0x0 0x08906000 0x0 0x400>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_qmpphy: phy@8907000 {
+ compatible = "qcom,qcs8300-qmp-usb3-uni-phy";
+ reg = <0x0 0x8907000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB_CLKREF_EN>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb3_prim_phy_pipe_clk_src";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
+ reg = <0x0 0x0a6f8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ wakeup-source;
+
+ status = "disabled";
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x0a600000 0x0 0xe000>;
+ interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x80 0x0>;
+ phys = <&usb_1_hsphy>, <&usb_qmpphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ };
+ };
+
+ usb_2: usb@a4f8800 {
+ compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
+ reg = <0x0 0x0a4f8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_SLEEP_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <120000000>;
+
+ interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
+
+ power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB20_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ status = "disabled";
+
+ usb_2_dwc3: usb@a400000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x0a400000 0x0 0xe000>;
+ interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x20 0x0>;
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ };
+ };
};
arch_timer: timer {
--
2.34.1On Thu, Oct 10, 2024 at 01:26:35AM GMT, Krishna Kurapati wrote:
> Add support for USB controllers on QCS8300. The second
> controller is only High Speed capable.
>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 165 ++++++++++++++++++++++++++
> 1 file changed, 165 insertions(+)
[...]
> +
> + usb_2: usb@a4f8800 {
> + compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
> + reg = <0x0 0x0a4f8800 0x0 0x400>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
> + <&gcc GCC_USB20_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
> + <&gcc GCC_USB20_SLEEP_CLK>,
> + <&gcc GCC_USB20_MOCK_UTMI_CLK>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi";
> +
> + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB20_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <120000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
> + interrupt-names = "pwr_event",
> + "hs_phy_irq",
> + "dp_hs_phy_irq",
> + "dm_hs_phy_irq";
> +
> + power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
> + required-opps = <&rpmhpd_opp_nom>;
> +
> + resets = <&gcc GCC_USB20_PRIM_BCR>;
> +
> + interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
> + interconnect-names = "usb-ddr", "apps-usb";
As this is a USB2-only host, shouldn't it also have qcom,select-utmi-as-pipe-clk ?
> +
> + status = "disabled";
> +
> + usb_2_dwc3: usb@a400000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x0a400000 0x0 0xe000>;
> + interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0x20 0x0>;
> + phys = <&usb_2_hsphy>;
> + phy-names = "usb2-phy";
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + };
> + };
> };
>
> arch_timer: timer {
> --
> 2.34.1
>
--
With best wishes
Dmitry
On 10/10/2024 7:52 PM, Dmitry Baryshkov wrote:
> On Thu, Oct 10, 2024 at 01:26:35AM GMT, Krishna Kurapati wrote:
>> Add support for USB controllers on QCS8300. The second
>> controller is only High Speed capable.
>>
>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 165 ++++++++++++++++++++++++++
>> 1 file changed, 165 insertions(+)
>
> [...]
>
>> +
>> + usb_2: usb@a4f8800 {
>> + compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
>> + reg = <0x0 0x0a4f8800 0x0 0x400>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
>> + <&gcc GCC_USB20_MASTER_CLK>,
>> + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
>> + <&gcc GCC_USB20_SLEEP_CLK>,
>> + <&gcc GCC_USB20_MOCK_UTMI_CLK>;
>> + clock-names = "cfg_noc",
>> + "core",
>> + "iface",
>> + "sleep",
>> + "mock_utmi";
>> +
>> + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
>> + <&gcc GCC_USB20_MASTER_CLK>;
>> + assigned-clock-rates = <19200000>, <120000000>;
>> +
>> + interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
>> + <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
>> + <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
>> + <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
>> + interrupt-names = "pwr_event",
>> + "hs_phy_irq",
>> + "dp_hs_phy_irq",
>> + "dm_hs_phy_irq";
>> +
>> + power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> +
>> + resets = <&gcc GCC_USB20_PRIM_BCR>;
>> +
>> + interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
>> + interconnect-names = "usb-ddr", "apps-usb";
>
> As this is a USB2-only host, shouldn't it also have qcom,select-utmi-as-pipe-clk ?
>
Hi Dmitry,
Thanks for the catch. You are right, it needs to be added according to
bindings. Since I would be sending another patch after this series to
enable the second controller, would it be fine if I add it in that patch
or do you suggest updating this one.
Also I see some others are not using it as well, like sc7280 which also
might need to be updated.
Regards,
Krishna,
>> +
>> + status = "disabled";
>> +
>> + usb_2_dwc3: usb@a400000 {
>> + compatible = "snps,dwc3";
>> + reg = <0x0 0x0a400000 0x0 0xe000>;
>> + interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
>> + iommus = <&apps_smmu 0x20 0x0>;
>> + phys = <&usb_2_hsphy>;
>> + phy-names = "usb2-phy";
>> + snps,dis_u2_susphy_quirk;
>> + snps,dis_enblslpm_quirk;
>> + };
>> + };
>> };
>>
>> arch_timer: timer {
>> --
>> 2.34.1
>>
>
On Thu, 10 Oct 2024 at 17:57, Krishna Kurapati
<quic_kriskura@quicinc.com> wrote:
>
>
>
> On 10/10/2024 7:52 PM, Dmitry Baryshkov wrote:
> > On Thu, Oct 10, 2024 at 01:26:35AM GMT, Krishna Kurapati wrote:
> >> Add support for USB controllers on QCS8300. The second
> >> controller is only High Speed capable.
> >>
> >> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 165 ++++++++++++++++++++++++++
> >> 1 file changed, 165 insertions(+)
> >
> > [...]
> >
> >> +
> >> + usb_2: usb@a4f8800 {
> >> + compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
> >> + reg = <0x0 0x0a4f8800 0x0 0x400>;
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> + ranges;
> >> +
> >> + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
> >> + <&gcc GCC_USB20_MASTER_CLK>,
> >> + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
> >> + <&gcc GCC_USB20_SLEEP_CLK>,
> >> + <&gcc GCC_USB20_MOCK_UTMI_CLK>;
> >> + clock-names = "cfg_noc",
> >> + "core",
> >> + "iface",
> >> + "sleep",
> >> + "mock_utmi";
> >> +
> >> + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
> >> + <&gcc GCC_USB20_MASTER_CLK>;
> >> + assigned-clock-rates = <19200000>, <120000000>;
> >> +
> >> + interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
> >> + <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
> >> + <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
> >> + <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
> >> + interrupt-names = "pwr_event",
> >> + "hs_phy_irq",
> >> + "dp_hs_phy_irq",
> >> + "dm_hs_phy_irq";
> >> +
> >> + power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
> >> + required-opps = <&rpmhpd_opp_nom>;
> >> +
> >> + resets = <&gcc GCC_USB20_PRIM_BCR>;
> >> +
> >> + interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
> >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
> >> + interconnect-names = "usb-ddr", "apps-usb";
> >
> > As this is a USB2-only host, shouldn't it also have qcom,select-utmi-as-pipe-clk ?
> >
>
> Hi Dmitry,
>
> Thanks for the catch. You are right, it needs to be added according to
> bindings. Since I would be sending another patch after this series to
> enable the second controller, would it be fine if I add it in that patch
> or do you suggest updating this one.
I think it's better to fix it from the beginning.
>
> Also I see some others are not using it as well, like sc7280 which also
> might need to be updated.
Interesting enough I don't see this option being enabled on SC7280 platforms.
>
> Regards,
> Krishna,
>
> >> +
> >> + status = "disabled";
> >> +
> >> + usb_2_dwc3: usb@a400000 {
> >> + compatible = "snps,dwc3";
> >> + reg = <0x0 0x0a400000 0x0 0xe000>;
> >> + interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
> >> + iommus = <&apps_smmu 0x20 0x0>;
> >> + phys = <&usb_2_hsphy>;
> >> + phy-names = "usb2-phy";
> >> + snps,dis_u2_susphy_quirk;
> >> + snps,dis_enblslpm_quirk;
> >> + };
> >> + };
> >> };
> >>
> >> arch_timer: timer {
> >> --
> >> 2.34.1
> >>
> >
--
With best wishes
Dmitry
On 10/10/2024 8:42 PM, Dmitry Baryshkov wrote:
> On Thu, 10 Oct 2024 at 17:57, Krishna Kurapati
> <quic_kriskura@quicinc.com> wrote:
>>
[...]
>>>> + resets = <&gcc GCC_USB20_PRIM_BCR>;
>>>> +
>>>> + interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
>>>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
>>>> + interconnect-names = "usb-ddr", "apps-usb";
>>>
>>> As this is a USB2-only host, shouldn't it also have qcom,select-utmi-as-pipe-clk ?
>>>
>>
>> Hi Dmitry,
>>
>> Thanks for the catch. You are right, it needs to be added according to
>> bindings. Since I would be sending another patch after this series to
>> enable the second controller, would it be fine if I add it in that patch
>> or do you suggest updating this one.
>
> I think it's better to fix it from the beginning.
>
Ok, Will send a v2 adding this quirk.
Can you also help review the DTS change. So that I can carry forward and
RB Tags I get to v2.
Regards,
Krishna,
>>
>> Also I see some others are not using it as well, like sc7280 which also
>> might need to be updated.
>
> Interesting enough I don't see this option being enabled on SC7280 platforms.
>
>>
>> Regards,
>> Krishna,
>>
>>>> +
>>>> + status = "disabled";
>>>> +
>>>> + usb_2_dwc3: usb@a400000 {
>>>> + compatible = "snps,dwc3";
>>>> + reg = <0x0 0x0a400000 0x0 0xe000>;
>>>> + interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
>>>> + iommus = <&apps_smmu 0x20 0x0>;
>>>> + phys = <&usb_2_hsphy>;
>>>> + phy-names = "usb2-phy";
>>>> + snps,dis_u2_susphy_quirk;
>>>> + snps,dis_enblslpm_quirk;
>>>> + };
>>>> + };
>>>> };
>>>>
>>>> arch_timer: timer {
>>>> --
>>>> 2.34.1
>>>>
>>>
>
>
>
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