From nobody Wed Nov 27 15:36:24 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 879571E0E15; Wed, 9 Oct 2024 19:56:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728503821; cv=none; b=SLrjIUtino9gxqxQhHoVvDHP7tuFaKzoh5bn6kwUmxDKz1Ey8NE4jS/fW/9ACBkKFz3px0qUz6bB7nDPeaYSnF7WlKpHKknrSNZwkMq728iEaQ/me+cOUu8onbo+UUr2hkpgNrtunca8lGTq21dm9gJpwO/i2X/5kGKwF/+vZWM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728503821; c=relaxed/simple; bh=gP3+8UloI0jIAK9s82nd6zd2eQ1pgk0yh2OZ8n6OHzY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YMypQ7hjIMf4O/Wf3ExNNe5+Nod+ee1V1N6N1rOMDYgKig/Y6tNiBTP5FN2p7GV+IfT/D/ChEZf0gvUV47UMyad2GEfSlrCv+4tWBgprd/ztxTC7mmeGEhDJaAM9fnvXyUkV84pCCcWgcdxmStT2FE+hJls1YLCQxzWvYgBKSFE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Vc2kgICL; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Vc2kgICL" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 499Dp7e6029281; Wed, 9 Oct 2024 19:56:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= +KdTWw8PMXjIa1o8WeCRr3hFTvtWOL6/9Ip+78GtCD0=; b=Vc2kgICLwQL5KZTc f8Jay2noaUS2GrkEIGDNCZ2gy/BuYP/+VGAgA5Z+erj33fMvYFXZFXUXl0QtkSjB Ysv9PO1KRg5EtqdaPLsP5lionl6JafO0qIu292V6fB8PNkAj0Rnn9Pdta+Le/CK/ 367FQhvmlkMuYjdNQi3GoShMQHjHKjSYqaliHMv6ZmYZXk72q1s/j/lVWk8CQojE q+eBylT2jxyIlU6+89PCW+wJrZtScLcPIxD94msHblYEL0qS8aLaFIVqKYRfM05e U0Du8ixWnrZZ3g3sPilMmMCQVyRRaGvVcFKZ3XKHjUOKkiZxFGIpr68cmh+T3+f5 VyHYzA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 424yj0645n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 19:56:56 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 499JusbG006885 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Oct 2024 19:56:54 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 12:56:51 -0700 From: Krishna Kurapati To: Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Konrad Dybcio , Conor Dooley CC: , , , , , Krishna Kurapati Subject: [PATCH 1/2] arm64: dts: qcom: Add support for usb nodes on QCS8300 Date: Thu, 10 Oct 2024 01:26:35 +0530 Message-ID: <20241009195636.2649952-2-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009195636.2649952-1-quic_kriskura@quicinc.com> References: <20241009195636.2649952-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: A9LWYsiTYSLt4IxX1XBW8vjxu4wQCbuD X-Proofpoint-ORIG-GUID: A9LWYsiTYSLt4IxX1XBW8vjxu4wQCbuD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 priorityscore=1501 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090124 Content-Type: text/plain; charset="utf-8" Add support for USB controllers on QCS8300. The second controller is only High Speed capable. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 165 ++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 2c35f96c3f28..701b834e9b58 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -1363,6 +1363,171 @@ IPCC_MPROC_SIGNAL_GLINK_QMP qcom,remote-pid =3D <5>; }; }; + + usb_1_hsphy: phy@8904000 { + compatible =3D "qcom,qcs8300-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg =3D <0x0 0x8904000 0x0 0x400>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_USB2_PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy: phy@8906000 { + compatible =3D "qcom,qcs8300-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg =3D <0x0 0x08906000 0x0 0x400>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_USB2_PHY_SEC_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_qmpphy: phy@8907000 { + compatible =3D "qcom,qcs8300-qmp-usb3-uni-phy"; + reg =3D <0x0 0x8907000 0x0 0x2000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", "ref", "com_aux", "pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names =3D "phy", "phy_phy"; + + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "usb3_prim_phy_pipe_clk_src"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible =3D "qcom,qcs8300-dwc3", "qcom,dwc3"; + reg =3D <0x0 0x0a6f8800 0x0 0x400>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + interconnects =3D <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + wakeup-source; + + status =3D "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible =3D "snps,dwc3"; + reg =3D <0x0 0x0a600000 0x0 0xe000>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x80 0x0>; + phys =3D <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + }; + }; + + usb_2: usb@a4f8800 { + compatible =3D "qcom,qcs8300-dwc3", "qcom,dwc3"; + reg =3D <0x0 0x0a4f8800 0x0 0x400>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <120000000>; + + interrupts-extended =3D <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_BOTH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + power-domains =3D <&gcc GCC_USB20_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB20_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + status =3D "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible =3D "snps,dwc3"; + reg =3D <0x0 0x0a400000 0x0 0xe000>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x20 0x0>; + phys =3D <&usb_2_hsphy>; + phy-names =3D "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + }; + }; }; =20 arch_timer: timer { --=20 2.34.1