IBS Fetch and IBS Op pmus have constraints on sample period. The sample
period is verified at the time of opening an event but not at the ioctl()
interface. Hence, a user can open an event with valid period but change
it later with ioctl(). Add a ->check_period() callback to verify the
period provided at ioctl() is also valid.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
---
 arch/x86/events/amd/ibs.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index e7522ba45a7e..33728ed6d7a6 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -551,6 +551,28 @@ static void perf_ibs_del(struct perf_event *event, int flags)
 
 static void perf_ibs_read(struct perf_event *event) { }
 
+static int perf_ibs_check_period(struct perf_event *event, u64 value)
+{
+	struct perf_ibs *perf_ibs;
+	u64 low_nibble;
+
+	if (event->attr.freq)
+		return 0;
+
+	perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
+	low_nibble = value & 0xFULL;
+
+	/*
+	 * This contradicts with perf_ibs_init() which allows sample period
+	 * with lower nibble bits set but silently masks them off. Whereas
+	 * this returns error.
+	 */
+	if (low_nibble || value < perf_ibs->min_period)
+		return -EINVAL;
+
+	return 0;
+}
+
 /*
  * We need to initialize with empty group if all attributes in the
  * group are dynamic.
@@ -676,6 +698,7 @@ static struct perf_ibs perf_ibs_fetch = {
 		.start		= perf_ibs_start,
 		.stop		= perf_ibs_stop,
 		.read		= perf_ibs_read,
+		.check_period	= perf_ibs_check_period,
 		.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
 	},
 	.msr			= MSR_AMD64_IBSFETCHCTL,
@@ -701,6 +724,7 @@ static struct perf_ibs perf_ibs_op = {
 		.start		= perf_ibs_start,
 		.stop		= perf_ibs_stop,
 		.read		= perf_ibs_read,
+		.check_period	= perf_ibs_check_period,
 		.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
 	},
 	.msr			= MSR_AMD64_IBSOPCTL,
-- 
2.46.2

On Mon, Oct 07, 2024 at 03:48:09AM +0000, Ravi Bangoria wrote:
> IBS Fetch and IBS Op pmus have constraints on sample period. The sample
> period is verified at the time of opening an event but not at the ioctl()
> interface. Hence, a user can open an event with valid period but change
> it later with ioctl(). Add a ->check_period() callback to verify the
> period provided at ioctl() is also valid.
> 
> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
> ---
>  arch/x86/events/amd/ibs.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
> index e7522ba45a7e..33728ed6d7a6 100644
> --- a/arch/x86/events/amd/ibs.c
> +++ b/arch/x86/events/amd/ibs.c
> @@ -551,6 +551,28 @@ static void perf_ibs_del(struct perf_event *event, int flags)
>  
>  static void perf_ibs_read(struct perf_event *event) { }
>  
> +static int perf_ibs_check_period(struct perf_event *event, u64 value)
> +{
> +	struct perf_ibs *perf_ibs;
> +	u64 low_nibble;
> +
> +	if (event->attr.freq)
> +		return 0;
> +
> +	perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
> +	low_nibble = value & 0xFULL;
> +
> +	/*
> +	 * This contradicts with perf_ibs_init() which allows sample period
> +	 * with lower nibble bits set but silently masks them off. Whereas
> +	 * this returns error.
> +	 */
> +	if (low_nibble || value < perf_ibs->min_period)
> +		return -EINVAL;

You may want to check max_period too.

Thanks,
Namhyung

> +
> +	return 0;
> +}
> +
>  /*
>   * We need to initialize with empty group if all attributes in the
>   * group are dynamic.
> @@ -676,6 +698,7 @@ static struct perf_ibs perf_ibs_fetch = {
>  		.start		= perf_ibs_start,
>  		.stop		= perf_ibs_stop,
>  		.read		= perf_ibs_read,
> +		.check_period	= perf_ibs_check_period,
>  		.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
>  	},
>  	.msr			= MSR_AMD64_IBSFETCHCTL,
> @@ -701,6 +724,7 @@ static struct perf_ibs perf_ibs_op = {
>  		.start		= perf_ibs_start,
>  		.stop		= perf_ibs_stop,
>  		.read		= perf_ibs_read,
> +		.check_period	= perf_ibs_check_period,
>  		.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
>  	},
>  	.msr			= MSR_AMD64_IBSOPCTL,
> -- 
> 2.46.2
>