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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000252A4.mail.protection.outlook.com (10.167.242.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Mon, 7 Oct 2024 03:49:25 +0000 Received: from BLR-L-RBANGORI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 6 Oct 2024 22:49:19 -0500 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH 7/8] perf/amd/ibs: Add ->check_period() callback Date: Mon, 7 Oct 2024 03:48:09 +0000 Message-ID: <20241007034810.754-8-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241007034810.754-1-ravi.bangoria@amd.com> References: <20241007034810.754-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|IA1PR12MB7568:EE_ X-MS-Office365-Filtering-Correlation-Id: d88d0425-f8d3-4fb1-b51a-08dce6830998 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|1800799024|82310400026|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 03:49:25.5093 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d88d0425-f8d3-4fb1-b51a-08dce6830998 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7568 Content-Type: text/plain; charset="utf-8" IBS Fetch and IBS Op pmus have constraints on sample period. The sample period is verified at the time of opening an event but not at the ioctl() interface. Hence, a user can open an event with valid period but change it later with ioctl(). Add a ->check_period() callback to verify the period provided at ioctl() is also valid. Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index e7522ba45a7e..33728ed6d7a6 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -551,6 +551,28 @@ static void perf_ibs_del(struct perf_event *event, int= flags) =20 static void perf_ibs_read(struct perf_event *event) { } =20 +static int perf_ibs_check_period(struct perf_event *event, u64 value) +{ + struct perf_ibs *perf_ibs; + u64 low_nibble; + + if (event->attr.freq) + return 0; + + perf_ibs =3D container_of(event->pmu, struct perf_ibs, pmu); + low_nibble =3D value & 0xFULL; + + /* + * This contradicts with perf_ibs_init() which allows sample period + * with lower nibble bits set but silently masks them off. Whereas + * this returns error. + */ + if (low_nibble || value < perf_ibs->min_period) + return -EINVAL; + + return 0; +} + /* * We need to initialize with empty group if all attributes in the * group are dynamic. @@ -676,6 +698,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .start =3D perf_ibs_start, .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, + .check_period =3D perf_ibs_check_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSFETCHCTL, @@ -701,6 +724,7 @@ static struct perf_ibs perf_ibs_op =3D { .start =3D perf_ibs_start, .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, + .check_period =3D perf_ibs_check_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSOPCTL, --=20 2.46.2