This patch series introduces support for the second Root Port controller in
the Xilinx Versal Premium CPM5 block. The Versal Premium platform features
two Type-A Root Port controllers operating at Gen5 speed. However, the
error interrupt registers and their corresponding bits are located at
different offsets for Controller 0 and Controller 1.

To handle these differences, the series includes:

A new compatible string for the second Root Port controller in the device
tree bindings.

Driver updates to manage platform-specific interrupt registers and offsets
for both controllers using the new compatible string.

Thippeswamy Havalige (2):
  dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 host1
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port controller 1

 .../bindings/pci/xilinx-versal-cpm.yaml       |  1 +
 drivers/pci/controller/pcie-xilinx-cpm.c      | 50 +++++++++++++++----
 2 files changed, 40 insertions(+), 11 deletions(-)

-- 
2.34.1

Hello,

> This patch series introduces support for the second Root Port controller in
> the Xilinx Versal Premium CPM5 block. The Versal Premium platform features
> two Type-A Root Port controllers operating at Gen5 speed. However, the
> error interrupt registers and their corresponding bits are located at
> different offsets for Controller 0 and Controller 1.
> 
> To handle these differences, the series includes:
> 
> A new compatible string for the second Root Port controller in the device
> tree bindings.
> 
> Driver updates to manage platform-specific interrupt registers and offsets
> for both controllers using the new compatible string.

Applied to controller/xilinx-cpm, thank you!

[01/02] dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 host1
        https://git.kernel.org/pci/pci/c/5c911b4659d5

[02/02] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port Controller 1
        https://git.kernel.org/pci/pci/c/

	Krzysztof