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Sun, 22 Sep 2024 01:14:26 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , , , Thippeswamy Havalige Subject: [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 host1 Date: Sun, 22 Sep 2024 11:43:17 +0530 Message-ID: <20240922061318.2653503-2-thippesw@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240922061318.2653503-1-thippesw@amd.com> References: <20240922061318.2653503-1-thippesw@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6731:EE_|MN0PR12MB6054:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c07f074-d7e3-4127-3835-08dcdacdd2b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6oPTm6Kf46R5FmntKf5iUIcrfdqE0d7Z11yY9m1Lgi47eZC/OB5D73GlSPN+?= =?us-ascii?Q?GMFn1ddOOt+pJz4mhjs/j53S6zpww1LIePrKVdWi6ivUMRC5p0qZpNW27fWS?= =?us-ascii?Q?H7EzrDnsV8gkGNWVaNktgLkqizBDaZdxKnVgRg6w5Azov3mffPKQznUPTZ13?= =?us-ascii?Q?xgDmJAlZh6ggWjypQ1cx2ubPiGtkxezu2qbNiyhSX1dRNa8lQy6O35pVw31H?= =?us-ascii?Q?O3VOrrWUrQjT8cv/O/fDzIrd9gPfE91UIjSN4srQR2kl3UY/g8HBL4tIfxZ5?= =?us-ascii?Q?/oQJ3ysuhWjg3gJviyEW/lzd6f3xPyhMFz/hVmvhwR9+0RXJ7fggI1fsHfTM?= =?us-ascii?Q?V04MrinO/V7rZ7+xs0y/yiLgpBY1g1s7gzvWJfFNE7Mr/kYPo5+Iir+jNcSW?= =?us-ascii?Q?gGShEMEX0SAUiw9z4g4ERr7kVc8YpJq/cFcVY/dIlGSUM1qjguAVYtngk8tu?= =?us-ascii?Q?4zftLMUSpOeOie4ty+FG/udnToopICX8QEVBV0brl05PoPukzp+pDz+BQayG?= =?us-ascii?Q?tfWdgZcf+wDsPBVKrw6T72ELPnMmHCxLatuQw0JEkR7JaMR41u2HC1Yi/eX9?= =?us-ascii?Q?i3L/r2YZ9luMhGcQ1RlQ7s0nbEVHbQuHGTfg3Lqn4D9H3wGOWNcoBpdjDvzg?= =?us-ascii?Q?H9XoDbCDxiC0t7IAWRdlermA06/jPfNOBiqzYj9VT8L895P/jfq9KU3GtI1p?= =?us-ascii?Q?knM1mrR4BETtvS3Frpn5TJ+4j5UWKMJYQza4gUDr5mHkX6bxSjy8IzDfBB1i?= =?us-ascii?Q?na4woz5KHIvoCWaQGjxcPjgdIBa+Igus4GR9kENAv6yfSuVRsnlu3f2WggfJ?= =?us-ascii?Q?crYiyyHOsRSlNiPeiC2fW6tAFVN0DC8J8wUCmIMj0sQwbo9eEbGrEiDEPe/4?= =?us-ascii?Q?X+GAIjVyXXeq0CBTfiEBBQLzhNeobKFaKD6RgPMmOILw7l/iH5pHx3LoMqRd?= =?us-ascii?Q?x4mwVJK3FhSjI4WY8LmSj4OpGoui64GbnRPZMQ3bS5imIpTeHH06jDW9MAk8?= =?us-ascii?Q?H6Mhf9C9r9hhLkNKmVJC6p3zK5O861goXG03MRCLxeax82UM4+NPlSONHWxC?= =?us-ascii?Q?aBG+16d/rBuz6rRHog3TW66WhfAqMNO8MOBzzWyXyZA7lRnywkZWcTIQ6Cpv?= =?us-ascii?Q?KNev+a24Lq6Z2xtSRCGjXqNL7iTFCS2WiMkZLnZrVeL5l7q8Z5ND9FEwmjGB?= =?us-ascii?Q?MYqG8F5VRR6S7c6Xu+5rqDxZsJvqceokr8SnavieiqOzwo9kdXXUlNOgpPXL?= =?us-ascii?Q?IfgZoRf4bCRPpMS4uvLM+Fp8EI1ItIO3YIcykAY1SFY0D+F+YG6JHReNFFdq?= =?us-ascii?Q?IUgV2l2QJ4S5gqRiDU9OUWIZKoeOJin+kDltEXAZEUUTWTSPJwjVMSwiCtRu?= =?us-ascii?Q?1PYJZbgv0QNY4U6MZtewzt5P9SuZJv7CaG6lshHnnObRMkYRQYwVUvJow4EN?= =?us-ascii?Q?Thwah1iTJkW2kTVKx1GNC95uXL3184dO?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2024 06:14:31.6069 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c07f074-d7e3-4127-3835-08dcdacdd2b4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6731.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6054 Content-Type: text/plain; charset="utf-8" The Xilinx Versal premium series has CPM5 block which supports two typeA Root Port controller functionality at Gen5 speed. Add compatible string to distinguish between two CPM5 rootport controller1. since Legacy and error interrupt register and bits for both the controllers are at different offsets. Signed-off-by: Thippeswamy Havalige Acked-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam --- changes in v3: -------------- 1. Modify compatible string. --- Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b= /Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 989fb0fa2577..b63a759ec2d7 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -17,6 +17,7 @@ properties: enum: - xlnx,versal-cpm-host-1.00 - xlnx,versal-cpm5-host + - xlnx,versal-cpm5-host1 =20 reg: items: --=20 2.34.1 From nobody Fri Nov 29 10:40:13 2024 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2064.outbound.protection.outlook.com [40.107.236.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A87619341D; Sun, 22 Sep 2024 06:14:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2024 06:14:35.5461 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b8dfd2b-545a-45ec-5f2b-08dcdacdd501 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7547 Content-Type: text/plain; charset="utf-8" Add support for the Xilinx Versal CPM5 Root Port Controller 1. The key difference between Controller 0 and Controller 1 lies in the platform-specific error interrupt bits, which are located at different register offsets. To handle these differences, updated variant structure to hold the following platform-specific details: - Interrupt status register offset (ir_status) - Interrupt enable register offset (ir_enable) - Miscellaneous interrupt values (ir_misc_value) The driver differentiates between Controller 0 and Controller 1 using the compatible string in the device tree. This ensures that the appropriate register offsets are used for each controller, allowing for correct handling of platform-specific interrupts and initialization. Signed-off-by: Thippeswamy Havalige Reviewed-by: Manivannan Sadhasivam --- changes in v3: -------------- 1. Add kernel Documentation for variant structure. 2. Modify compatible string. changes in v2: -------------- 1. Introduced new constants for Controller 1. 2. Extended the xilinx_cpm_variant structure to support a. ir_status, b. ir_enable, and=20 c. ir_misc_value for different controllers. 3. Updated IRQ handling and initialization to use the variant structure. 4. Added a new device tree match entry for Controller 1. --- drivers/pci/controller/pcie-xilinx-cpm.c | 50 ++++++++++++++++++------ 1 file changed, 39 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/control= ler/pcie-xilinx-cpm.c index a0f5e1d67b04..81e8bfae53d0 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -30,11 +30,14 @@ #define XILINX_CPM_PCIE_REG_IDRN_MASK 0x00000E3C #define XILINX_CPM_PCIE_MISC_IR_STATUS 0x00000340 #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348 -#define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1) +#define XILINX_CPM_PCIE0_MISC_IR_LOCAL BIT(1) +#define XILINX_CPM_PCIE1_MISC_IR_LOCAL BIT(2) =20 -#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0 -#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 -#define XILINX_CPM_PCIE_IR_LOCAL BIT(0) +#define XILINX_CPM_PCIE0_IR_STATUS 0x000002A0 +#define XILINX_CPM_PCIE1_IR_STATUS 0x000002B4 +#define XILINX_CPM_PCIE0_IR_ENABLE 0x000002A8 +#define XILINX_CPM_PCIE1_IR_ENABLE 0x000002BC +#define XILINX_CPM_PCIE_IR_LOCAL BIT(0) =20 #define IMR(x) BIT(XILINX_PCIE_INTR_ ##x) =20 @@ -80,14 +83,21 @@ enum xilinx_cpm_version { CPM, CPM5, + CPM5_HOST1, }; =20 /** * struct xilinx_cpm_variant - CPM variant information * @version: CPM version + * @ir_status: Offset for the error interrupt status register + * @ir_enable: Offset for the CPM5 local error interrupt enable register + * @ir_misc_value: A bitmask for the miscellaneous interrupt status */ struct xilinx_cpm_variant { enum xilinx_cpm_version version; + u32 ir_status; + u32 ir_enable; + u32 ir_misc_value; }; =20 /** @@ -269,6 +279,7 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc = *desc) { struct xilinx_cpm_pcie *port =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); + const struct xilinx_cpm_variant *variant =3D port->variant; unsigned long val; int i; =20 @@ -279,11 +290,11 @@ static void xilinx_cpm_pcie_event_flow(struct irq_des= c *desc) generic_handle_domain_irq(port->cpm_domain, i); pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR); =20 - if (port->variant->version =3D=3D CPM5) { - val =3D readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS); + if (variant->ir_status) { + val =3D readl_relaxed(port->cpm_base + variant->ir_status); if (val) writel_relaxed(val, port->cpm_base + - XILINX_CPM_PCIE_IR_STATUS); + variant->ir_status); } =20 /* @@ -465,6 +476,8 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie = *port) */ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) { + const struct xilinx_cpm_variant *variant =3D port->variant; + if (cpm_pcie_link_up(port)) dev_info(port->dev, "PCIe Link is UP\n"); else @@ -483,15 +496,15 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_c= pm_pcie *port) * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to * CPM SLCR block. */ - writel(XILINX_CPM_PCIE_MISC_IR_LOCAL, + writel(variant->ir_misc_value, port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); =20 - if (port->variant->version =3D=3D CPM5) { + if (variant->ir_enable) { writel(XILINX_CPM_PCIE_IR_LOCAL, - port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE); + port->cpm_base + variant->ir_enable); } =20 - /* Enable the Bridge enable bit */ + /* Set Bridge enable bit */ pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | XILINX_CPM_PCIE_REG_RPSC_BEN, XILINX_CPM_PCIE_REG_RPSC); @@ -609,10 +622,21 @@ static int xilinx_cpm_pcie_probe(struct platform_devi= ce *pdev) =20 static const struct xilinx_cpm_variant cpm_host =3D { .version =3D CPM, + .ir_misc_value =3D XILINX_CPM_PCIE0_MISC_IR_LOCAL, }; =20 static const struct xilinx_cpm_variant cpm5_host =3D { .version =3D CPM5, + .ir_misc_value =3D XILINX_CPM_PCIE0_MISC_IR_LOCAL, + .ir_status =3D XILINX_CPM_PCIE0_IR_STATUS, + .ir_enable =3D XILINX_CPM_PCIE0_IR_ENABLE, +}; + +static const struct xilinx_cpm_variant cpm5_host1 =3D { + .version =3D CPM5_HOST1, + .ir_misc_value =3D XILINX_CPM_PCIE1_MISC_IR_LOCAL, + .ir_status =3D XILINX_CPM_PCIE1_IR_STATUS, + .ir_enable =3D XILINX_CPM_PCIE1_IR_ENABLE, }; =20 static const struct of_device_id xilinx_cpm_pcie_of_match[] =3D { @@ -624,6 +648,10 @@ static const struct of_device_id xilinx_cpm_pcie_of_ma= tch[] =3D { .compatible =3D "xlnx,versal-cpm5-host", .data =3D &cpm5_host, }, + { + .compatible =3D "xlnx,versal-cpm5-host1", + .data =3D &cpm5_host1, + }, {} }; =20 --=20 2.34.1