Hi, Shawn:
On Fri, 2024-06-14 at 10:46 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <shawn.sung@mediatek.com>
>
> Set the plane alpha according to DRM plane property.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 1923bbd96014..2316d4a6dca7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -450,8 +450,10 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
> }
>
> con = ovl_fmt_convert(ovl, fmt);
> - if (state->base.fb && state->base.fb->format->has_alpha)
> - con |= OVL_CON_AEN | OVL_CON_ALPHA;
> + if (state->base.fb) {
> + con |= OVL_CON_AEN;
> + con |= state->base.alpha & OVL_CON_ALPHA;
> + }
>
> /* CONST_BLD must be enabled for XRGB formats although the alpha channel
> * can be ignored, or OVL will still read the value from memory.