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[PATCH v6 01/49] crypto: x86/aes-xts - Switch to new Intel CPU model defines

Tony Luck posted 49 patches 1 year, 7 months ago
There is a newer version of this series
[PATCH v6 01/49] crypto: x86/aes-xts - Switch to new Intel CPU model defines
Posted by Tony Luck 1 year, 7 months ago 
New CPU #defines encode vendor and family as well as model.

Signed-off-by: Tony Luck <tony.luck@intel.com>
---
 arch/x86/crypto/aesni-intel_glue.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index 5b25d2a58aeb..ef031655b2d3 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -1223,14 +1223,14 @@ DEFINE_XTS_ALG(vaes_avx10_512, "xts-aes-vaes-avx10_512", 800);
  * implementation with ymm registers (256-bit vectors) will be used instead.
  */
 static const struct x86_cpu_id zmm_exclusion_list[] = {
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_SKYLAKE_X },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_X },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_D },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_L },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_NNPI },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE_L },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE },
+	X86_MATCH_VFM(INTEL_SKYLAKE_X,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE_X,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE_D,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE_L,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE_NNPI,	0),
+	X86_MATCH_VFM(INTEL_TIGERLAKE_L,	0),
+	X86_MATCH_VFM(INTEL_TIGERLAKE,		0),
 	/* Allow Rocket Lake and later, and Sapphire Rapids and later. */
 	/* Also allow AMD CPUs (starting with Zen 4, the first with AVX-512). */
 	{},
-- 
2.45.0
Re: [PATCH v6 01/49] crypto: x86/aes-xts - Switch to new Intel CPU model defines
Posted by Borislav Petkov 1 year, 7 months ago 
+ Herbert as an FYI that I'll pick up this one and the next for 6.10 as
it is a fix for a regression that got discovered.

Thx.

On Mon, May 20, 2024 at 03:45:32PM -0700, Tony Luck wrote:
> New CPU #defines encode vendor and family as well as model.
> 
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> ---
>  arch/x86/crypto/aesni-intel_glue.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
> index 5b25d2a58aeb..ef031655b2d3 100644
> --- a/arch/x86/crypto/aesni-intel_glue.c
> +++ b/arch/x86/crypto/aesni-intel_glue.c
> @@ -1223,14 +1223,14 @@ DEFINE_XTS_ALG(vaes_avx10_512, "xts-aes-vaes-avx10_512", 800);
>   * implementation with ymm registers (256-bit vectors) will be used instead.
>   */
>  static const struct x86_cpu_id zmm_exclusion_list[] = {
> -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_SKYLAKE_X },
> -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_X },
> -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_D },
> -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE },
> -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_L },
> -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_NNPI },
> -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE_L },
> -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE },
> +	X86_MATCH_VFM(INTEL_SKYLAKE_X,		0),
> +	X86_MATCH_VFM(INTEL_ICELAKE_X,		0),
> +	X86_MATCH_VFM(INTEL_ICELAKE_D,		0),
> +	X86_MATCH_VFM(INTEL_ICELAKE,		0),
> +	X86_MATCH_VFM(INTEL_ICELAKE_L,		0),
> +	X86_MATCH_VFM(INTEL_ICELAKE_NNPI,	0),
> +	X86_MATCH_VFM(INTEL_TIGERLAKE_L,	0),
> +	X86_MATCH_VFM(INTEL_TIGERLAKE,		0),
>  	/* Allow Rocket Lake and later, and Sapphire Rapids and later. */
>  	/* Also allow AMD CPUs (starting with Zen 4, the first with AVX-512). */
>  	{},
> -- 

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette
Re: [PATCH v6 01/49] crypto: x86/aes-xts - Switch to new Intel CPU model defines
Posted by Herbert Xu 1 year, 7 months ago 
On Tue, May 21, 2024 at 07:22:02PM +0200, Borislav Petkov wrote:
> + Herbert as an FYI that I'll pick up this one and the next for 6.10 as
> it is a fix for a regression that got discovered.

Thanks.

> On Mon, May 20, 2024 at 03:45:32PM -0700, Tony Luck wrote:
> > New CPU #defines encode vendor and family as well as model.
> > 
> > Signed-off-by: Tony Luck <tony.luck@intel.com>
> > ---
> >  arch/x86/crypto/aesni-intel_glue.c | 16 ++++++++--------
> >  1 file changed, 8 insertions(+), 8 deletions(-)

Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Re: [PATCH v6 01/49] crypto: x86/aes-xts - Switch to new Intel CPU model defines
Posted by Eric Biggers 1 year, 7 months ago 
On Tue, May 21, 2024 at 07:22:02PM +0200, Borislav Petkov wrote:
> + Herbert as an FYI that I'll pick up this one and the next for 6.10 as
> it is a fix for a regression that got discovered.
> 
> Thx.
> 
> On Mon, May 20, 2024 at 03:45:32PM -0700, Tony Luck wrote:
> > New CPU #defines encode vendor and family as well as model.
> > 
> > Signed-off-by: Tony Luck <tony.luck@intel.com>
> > ---
> >  arch/x86/crypto/aesni-intel_glue.c | 16 ++++++++--------
> >  1 file changed, 8 insertions(+), 8 deletions(-)
> > 
> > diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
> > index 5b25d2a58aeb..ef031655b2d3 100644
> > --- a/arch/x86/crypto/aesni-intel_glue.c
> > +++ b/arch/x86/crypto/aesni-intel_glue.c
> > @@ -1223,14 +1223,14 @@ DEFINE_XTS_ALG(vaes_avx10_512, "xts-aes-vaes-avx10_512", 800);
> >   * implementation with ymm registers (256-bit vectors) will be used instead.
> >   */
> >  static const struct x86_cpu_id zmm_exclusion_list[] = {
> > -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_SKYLAKE_X },
> > -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_X },
> > -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_D },
> > -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE },
> > -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_L },
> > -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_NNPI },
> > -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE_L },
> > -	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE },
> > +	X86_MATCH_VFM(INTEL_SKYLAKE_X,		0),
> > +	X86_MATCH_VFM(INTEL_ICELAKE_X,		0),
> > +	X86_MATCH_VFM(INTEL_ICELAKE_D,		0),
> > +	X86_MATCH_VFM(INTEL_ICELAKE,		0),
> > +	X86_MATCH_VFM(INTEL_ICELAKE_L,		0),
> > +	X86_MATCH_VFM(INTEL_ICELAKE_NNPI,	0),
> > +	X86_MATCH_VFM(INTEL_TIGERLAKE_L,	0),
> > +	X86_MATCH_VFM(INTEL_TIGERLAKE,		0),
> >  	/* Allow Rocket Lake and later, and Sapphire Rapids and later. */
> >  	/* Also allow AMD CPUs (starting with Zen 4, the first with AVX-512). */
> >  	{},
> > -- 

Reviewed-by: Eric Biggers <ebiggers@google.com>

- Eric
[tip: x86/urgent] crypto: x86/aes-xts - switch to new Intel CPU model defines
Posted by tip-bot2 for Tony Luck 1 year, 7 months ago 
The following commit has been merged into the x86/urgent branch of tip:

Commit-ID:     6d85a058cf4941b5b2713b879ef41430e6aa74f3
Gitweb:        https://git.kernel.org/tip/6d85a058cf4941b5b2713b879ef41430e6aa74f3
Author:        Tony Luck <tony.luck@intel.com>
AuthorDate:    Mon, 20 May 2024 15:45:32 -07:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Wed, 22 May 2024 11:10:48 +02:00

crypto: x86/aes-xts - switch to new Intel CPU model defines

New CPU #defines encode vendor and family as well as model.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Eric Biggers <ebiggers@google.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Link: https://lore.kernel.org/r/20240520224620.9480-2-tony.luck@intel.com
---
 arch/x86/crypto/aesni-intel_glue.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index 5b25d2a..ef03165 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -1223,14 +1223,14 @@ DEFINE_XTS_ALG(vaes_avx10_512, "xts-aes-vaes-avx10_512", 800);
  * implementation with ymm registers (256-bit vectors) will be used instead.
  */
 static const struct x86_cpu_id zmm_exclusion_list[] = {
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_SKYLAKE_X },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_X },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_D },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_L },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_NNPI },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE_L },
-	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE },
+	X86_MATCH_VFM(INTEL_SKYLAKE_X,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE_X,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE_D,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE_L,		0),
+	X86_MATCH_VFM(INTEL_ICELAKE_NNPI,	0),
+	X86_MATCH_VFM(INTEL_TIGERLAKE_L,	0),
+	X86_MATCH_VFM(INTEL_TIGERLAKE,		0),
 	/* Allow Rocket Lake and later, and Sapphire Rapids and later. */
 	/* Also allow AMD CPUs (starting with Zen 4, the first with AVX-512). */
 	{},

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