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Peter Anvin" , "Peter Zijlstra (Intel)" , Uros Bizjak , Rick Edgecombe , Arnd Bergmann , Tony Luck , Mateusz Guzik , Thomas Renninger , Andi Kleen , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v6 01/49] crypto: x86/aes-xts - Switch to new Intel CPU model defines Date: Mon, 20 May 2024 15:45:32 -0700 Message-ID: <20240520224620.9480-2-tony.luck@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240520224620.9480-1-tony.luck@intel.com> References: <20240520224620.9480-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Acked-by: Herbert Xu Reviewed-by: Eric Biggers --- arch/x86/crypto/aesni-intel_glue.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-int= el_glue.c index 5b25d2a58aeb..ef031655b2d3 100644 --- a/arch/x86/crypto/aesni-intel_glue.c +++ b/arch/x86/crypto/aesni-intel_glue.c @@ -1223,14 +1223,14 @@ DEFINE_XTS_ALG(vaes_avx10_512, "xts-aes-vaes-avx10_= 512", 800); * implementation with ymm registers (256-bit vectors) will be used instea= d. */ static const struct x86_cpu_id zmm_exclusion_list[] =3D { - { .vendor =3D X86_VENDOR_INTEL, .family =3D 6, .model =3D INTEL_FAM6_SKYL= AKE_X }, - { .vendor =3D X86_VENDOR_INTEL, .family =3D 6, .model =3D INTEL_FAM6_ICEL= AKE_X }, - { .vendor =3D X86_VENDOR_INTEL, .family =3D 6, .model =3D INTEL_FAM6_ICEL= AKE_D }, - { .vendor =3D X86_VENDOR_INTEL, .family =3D 6, .model =3D INTEL_FAM6_ICEL= AKE }, - { .vendor =3D X86_VENDOR_INTEL, .family =3D 6, .model =3D INTEL_FAM6_ICEL= AKE_L }, - { .vendor =3D X86_VENDOR_INTEL, .family =3D 6, .model =3D INTEL_FAM6_ICEL= AKE_NNPI }, - { .vendor =3D X86_VENDOR_INTEL, .family =3D 6, .model =3D INTEL_FAM6_TIGE= RLAKE_L }, - { .vendor =3D X86_VENDOR_INTEL, .family =3D 6, .model =3D INTEL_FAM6_TIGE= RLAKE }, + X86_MATCH_VFM(INTEL_SKYLAKE_X, 0), + X86_MATCH_VFM(INTEL_ICELAKE_X, 0), + X86_MATCH_VFM(INTEL_ICELAKE_D, 0), + X86_MATCH_VFM(INTEL_ICELAKE, 0), + X86_MATCH_VFM(INTEL_ICELAKE_L, 0), + X86_MATCH_VFM(INTEL_ICELAKE_NNPI, 0), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, 0), + X86_MATCH_VFM(INTEL_TIGERLAKE, 0), /* Allow Rocket Lake and later, and Sapphire Rapids and later. */ /* Also allow AMD CPUs (starting with Zen 4, the first with AVX-512). */ {}, --=20 2.45.0