From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
patch [1/5] - Introduced compatible string for Agilex5 board.
patch [2/5] - Add Agilex5 reset ID definitions.
patch [3/5] - Add Agilex5 clock manager header and yaml file.
patch [4/5] - Reused and modified Agilex clock manager driver for
Agilex5 to avoid code duplication. This patch depends on patch 4.
patch [5/5] - Add device tree files for Agilex5 platform. This patch
depends on patch 1,2,3 & 4.
patch v2 changes:-
- Add separate discription and const for Agilex5 board in yaml file.
- Add reset ID definitions required for Agilex5 and reused
altr,rst-mgr-s10 bindings similar to Agilex.
- Instead of creating separate clock manager driver, re-use agilex clock
manager driver and modified it for agilex5 changes to avoid code
duplicate.
- Fixed device tree alignment issues and other build warnings.
Removed ethernet nodes as it will be included in a separate patch.
Niravkumar L Rabara (5):
dt-bindings: intel: Add Intel Agilex5 compatible
dt-bindings: reset: add reset IDs for Agilex5
dt-bindings: clock: add Intel Agilex5 clock manager
clk: socfpga: agilex: add clock driver for the Agilex5
arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA
.../bindings/arm/intel,socfpga.yaml | 5 +
.../bindings/clock/intel,agilex5-clkmgr.yaml | 41 ++
arch/arm64/boot/dts/intel/Makefile | 1 +
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 468 ++++++++++++++++++
.../boot/dts/intel/socfpga_agilex5_socdk.dts | 39 ++
drivers/clk/socfpga/clk-agilex.c | 433 +++++++++++++++-
.../dt-bindings/clock/intel,agilex5-clkmgr.h | 100 ++++
include/dt-bindings/reset/altr,rst-mgr-s10.h | 5 +-
8 files changed, 1089 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h
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2.25.1