From nobody Sat Feb 7 23:22:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87083C04E69 for ; Tue, 1 Aug 2023 01:05:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231492AbjHABFy (ORCPT ); Mon, 31 Jul 2023 21:05:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229522AbjHABFw (ORCPT ); Mon, 31 Jul 2023 21:05:52 -0400 Received: from mgamail.intel.com (unknown [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6733EE67; Mon, 31 Jul 2023 18:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690851951; x=1722387951; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FICTb653hGovszk2ZCogn8s97PB2ERvjcbdzCvjfVMY=; b=N0nMZftP+P47/rkU624R56NSln3D3M0B75BTTx7pPTSytyVQ+iHOORAw a399ESE06i3E4AY+A7PFu0XoFSS+1zTpJkheLfMFbtXNZuTceESqRI75b KsqjpMlOQ8U+fbb1N2uvCTyIq/3irmRxEsIErr49UoWM6/aFkFahb1jHK 49mf3jS0yd/UVAMkR7F4/Va6ZQvd8IhhZH0Ze9o9q6M4GUJwktAqyl4GY 6QOnkYWtd3tOPzfpewdBpl1iQVmJ2QMe6VbMBH1MsEvhPTiKZQzPpJcYS j6jeyhPO4t2iUBeFmpLBU9Wy+zPOQ79gnoykYO1MNWtfTnvGXyex4mHu0 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="372788025" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="372788025" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2023 18:03:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="818587475" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="818587475" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by FMSMGA003.fm.intel.com with ESMTP; 31 Jul 2023 18:03:55 -0700 From: niravkumar.l.rabara@intel.com To: niravkumar.l.rabara@intel.com Cc: adrian.ho.yin.ng@intel.com, andrew@lunn.ch, conor+dt@kernel.org, devicetree@vger.kernel.org, dinguyen@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, netdev@vger.kernel.org, p.zabel@pengutronix.de, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, wen.ping.teh@intel.com Subject: [PATCH v2 1/5] dt-bindings: intel: Add Intel Agilex5 compatible Date: Tue, 1 Aug 2023 09:02:30 +0800 Message-Id: <20230801010234.792557-2-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230801010234.792557-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> <20230801010234.792557-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Agilex5 is a new SoCFPGA in Intel Agilex SoCFPGA Family, include compatible string for Agilex5 SoCFPGA board. Reviewed-by: Dinh Nguyen Signed-off-by: Niravkumar L Rabara Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Doc= umentation/devicetree/bindings/arm/intel,socfpga.yaml index 4b4dcf551eb6..2ee0c740eb56 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -21,6 +21,11 @@ properties: - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex + - description: Agilex5 boards + items: + - enum: + - intel,socfpga-agilex5-socdk + - const: intel,socfpga-agilex5 =20 additionalProperties: true =20 --=20 2.25.1 From nobody Sat Feb 7 23:22:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D362EC001DF for ; Tue, 1 Aug 2023 01:06:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231572AbjHABGI (ORCPT ); Mon, 31 Jul 2023 21:06:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231515AbjHABGG (ORCPT ); Mon, 31 Jul 2023 21:06:06 -0400 Received: from mgamail.intel.com (unknown [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19166171B; Mon, 31 Jul 2023 18:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690851959; x=1722387959; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fZZm64ITvXBzesnZhVTHqUbu1ipk4ym1rIVVjHPXy88=; b=XJsKTnuiG4ffyjxHNlZ8UgMYRKty2yFfXi8DZUJ4oYnJzYrXfNvUNNjH 04MW3XcsU1znplkueylIxU0byaTFj56kPdk2si43BhyaeWjJs1BZFbgDZ f4T5sCgt3z/1xXQedAwEadOgAYgtcC23FbX3wMEWKl7C2KvPn3RQLuHYN eDX/7K8OmdXe7rAw5sXgRMnYrFSh44zA+0IDxXo2jSeES+/8F0XEg8tap KtdbeAWsR/twpUiXbsKYfCObqcuc6D/fOrWmWJ8ejp+gJAXnWGaZCTB70 zmQFDKtgmkxCBX72Jm69L2Wvyn0zrpWOj2ca0UihrRSeAOlTvZbnLOjqe A==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="372788111" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="372788111" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2023 18:04:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="818587536" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="818587536" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by FMSMGA003.fm.intel.com with ESMTP; 31 Jul 2023 18:04:00 -0700 From: niravkumar.l.rabara@intel.com To: niravkumar.l.rabara@intel.com Cc: adrian.ho.yin.ng@intel.com, andrew@lunn.ch, conor+dt@kernel.org, devicetree@vger.kernel.org, dinguyen@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, netdev@vger.kernel.org, p.zabel@pengutronix.de, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, wen.ping.teh@intel.com Subject: [PATCH v2 2/5] dt-bindings: reset: add reset IDs for Agilex5 Date: Tue, 1 Aug 2023 09:02:31 +0800 Message-Id: <20230801010234.792557-3-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230801010234.792557-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> <20230801010234.792557-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Add reset ID definitions required for Intel Agilex5 SoCFPGA, re-use altr,rst-mgr-s10.h as common header file similar S10 & Agilex. Reviewed-by: Dinh Nguyen Signed-off-by: Niravkumar L Rabara Acked-by: Conor Dooley --- include/dt-bindings/reset/altr,rst-mgr-s10.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bind= ings/reset/altr,rst-mgr-s10.h index 70ea3a09dbe1..04c4d0c6fd34 100644 --- a/include/dt-bindings/reset/altr,rst-mgr-s10.h +++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h @@ -63,12 +63,15 @@ #define I2C2_RESET 74 #define I2C3_RESET 75 #define I2C4_RESET 76 -/* 77-79 is empty */ +#define I3C0_RESET 77 +#define I3C1_RESET 78 +/* 79 is empty */ #define UART0_RESET 80 #define UART1_RESET 81 /* 82-87 is empty */ #define GPIO0_RESET 88 #define GPIO1_RESET 89 +#define WATCHDOG4_RESET 90 =20 /* BRGMODRST */ #define SOC2FPGA_RESET 96 --=20 2.25.1 From nobody Sat Feb 7 23:22:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E7A1C04E69 for ; Tue, 1 Aug 2023 01:06:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231557AbjHABGS (ORCPT ); Mon, 31 Jul 2023 21:06:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231538AbjHABGO (ORCPT ); Mon, 31 Jul 2023 21:06:14 -0400 Received: from mgamail.intel.com (unknown [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6337D1FC6; Mon, 31 Jul 2023 18:06:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690851964; x=1722387964; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+HBx97q/TDX2v9SZY9OVxvW6i5na9ozEq7t6pZwm570=; b=dvdk83iAXJoovSzPGkak/gSvGdLo7zldw2qzworOnrZYq6AhEt3GCDtd bblMCJtr97l0XjRXVy3MOudyO6bTZf5+kcL1RBa4nrQRiS6zolwvjp+UV u/dqBMv6+GSobXcSF0tS0QVLz26QCfAXthZJ2Edy8DL4qHELJCD86SMqj dOE9IpYHuEcV/2Ln54KqqdP/wf256QnnlM9rJ+V3MT+6P2YsC3QU71MuE x8d0trK9rBtJW8eWvC+SXjb3QF2fGhB33ElqEgKl/4oUXjn10SkhCEqZQ lRHV2FHjQgD1/wPy6nNCN221Ipkh7eXarFqdZteCjKiywZBpu376Hxgln Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="372788203" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="372788203" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2023 18:04:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="818587580" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="818587580" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by FMSMGA003.fm.intel.com with ESMTP; 31 Jul 2023 18:04:05 -0700 From: niravkumar.l.rabara@intel.com To: niravkumar.l.rabara@intel.com Cc: adrian.ho.yin.ng@intel.com, andrew@lunn.ch, conor+dt@kernel.org, devicetree@vger.kernel.org, dinguyen@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, netdev@vger.kernel.org, p.zabel@pengutronix.de, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, wen.ping.teh@intel.com Subject: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager Date: Tue, 1 Aug 2023 09:02:32 +0800 Message-Id: <20230801010234.792557-4-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230801010234.792557-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> <20230801010234.792557-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Add clock ID definitions for Intel Agilex5 SoCFPGA. The registers in Agilex5 handling the clock is named as clock manager. Signed-off-by: Teh Wen Ping Reviewed-by: Dinh Nguyen Signed-off-by: Niravkumar L Rabara Reviewed-by: Conor Dooley reviewed-by after all. --- .../bindings/clock/intel,agilex5-clkmgr.yaml | 41 +++++++ .../dt-bindings/clock/intel,agilex5-clkmgr.h | 100 ++++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5-c= lkmgr.yaml create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.y= aml b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml new file mode 100644 index 000000000000..60e57a9fb939 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Agilex5 clock manager + +maintainers: + - Dinh Nguyen + +description: + The Intel Agilex5 Clock Manager is an integrated clock controller, which + generates and supplies clock to all the modules. + +properties: + compatible: + const: intel,agilex5-clkmgr + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node: + - | + clkmgr: clock-controller@10d10000 { + compatible =3D "intel,agilex5-clkmgr"; + reg =3D <0x10d10000 0x1000>; + #clock-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/intel,agilex5-clkmgr.h b/include/dt-= bindings/clock/intel,agilex5-clkmgr.h new file mode 100644 index 000000000000..2f3a23b31c5c --- /dev/null +++ b/include/dt-bindings/clock/intel,agilex5-clkmgr.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2023, Intel Corporation + */ + +#ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H +#define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H + +/* fixed rate clocks */ +#define AGILEX5_OSC1 0 +#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX5_CB_INTOSC_LS_CLK 2 +#define AGILEX5_F2S_FREE_CLK 3 + +/* PLL clocks */ +#define AGILEX5_MAIN_PLL_CLK 4 +#define AGILEX5_MAIN_PLL_C0_CLK 5 +#define AGILEX5_MAIN_PLL_C1_CLK 6 +#define AGILEX5_MAIN_PLL_C2_CLK 7 +#define AGILEX5_MAIN_PLL_C3_CLK 8 +#define AGILEX5_PERIPH_PLL_CLK 9 +#define AGILEX5_PERIPH_PLL_C0_CLK 10 +#define AGILEX5_PERIPH_PLL_C1_CLK 11 +#define AGILEX5_PERIPH_PLL_C2_CLK 12 +#define AGILEX5_PERIPH_PLL_C3_CLK 13 +#define AGILEX5_CORE0_FREE_CLK 14 +#define AGILEX5_CORE1_FREE_CLK 15 +#define AGILEX5_CORE2_FREE_CLK 16 +#define AGILEX5_CORE3_FREE_CLK 17 +#define AGILEX5_DSU_FREE_CLK 18 +#define AGILEX5_BOOT_CLK 19 + +/* fixed factor clocks */ +#define AGILEX5_L3_MAIN_FREE_CLK 20 +#define AGILEX5_NOC_FREE_CLK 21 +#define AGILEX5_S2F_USR0_CLK 22 +#define AGILEX5_NOC_CLK 23 +#define AGILEX5_EMAC_A_FREE_CLK 24 +#define AGILEX5_EMAC_B_FREE_CLK 25 +#define AGILEX5_EMAC_PTP_FREE_CLK 26 +#define AGILEX5_GPIO_DB_FREE_CLK 27 +#define AGILEX5_S2F_USER0_FREE_CLK 28 +#define AGILEX5_S2F_USER1_FREE_CLK 29 +#define AGILEX5_PSI_REF_FREE_CLK 30 +#define AGILEX5_USB31_FREE_CLK 31 + +/* Gate clocks */ +#define AGILEX5_CORE0_CLK 32 +#define AGILEX5_CORE1_CLK 33 +#define AGILEX5_CORE2_CLK 34 +#define AGILEX5_CORE3_CLK 35 +#define AGILEX5_MPU_CLK 36 +#define AGILEX5_MPU_PERIPH_CLK 37 +#define AGILEX5_MPU_CCU_CLK 38 +#define AGILEX5_L4_MAIN_CLK 39 +#define AGILEX5_L4_MP_CLK 40 +#define AGILEX5_L4_SYS_FREE_CLK 41 +#define AGILEX5_L4_SP_CLK 42 +#define AGILEX5_CS_AT_CLK 43 +#define AGILEX5_CS_TRACE_CLK 44 +#define AGILEX5_CS_PDBG_CLK 45 +#define AGILEX5_EMAC1_CLK 47 +#define AGILEX5_EMAC2_CLK 48 +#define AGILEX5_EMAC_PTP_CLK 49 +#define AGILEX5_GPIO_DB_CLK 50 +#define AGILEX5_S2F_USER0_CLK 51 +#define AGILEX5_S2F_USER1_CLK 52 +#define AGILEX5_PSI_REF_CLK 53 +#define AGILEX5_USB31_SUSPEND_CLK 54 +#define AGILEX5_EMAC0_CLK 46 +#define AGILEX5_USB31_BUS_CLK_EARLY 55 +#define AGILEX5_USB2OTG_HCLK 56 +#define AGILEX5_SPIM_0_CLK 57 +#define AGILEX5_SPIM_1_CLK 58 +#define AGILEX5_SPIS_0_CLK 59 +#define AGILEX5_SPIS_1_CLK 60 +#define AGILEX5_DMA_CORE_CLK 61 +#define AGILEX5_DMA_HS_CLK 62 +#define AGILEX5_I3C_0_CORE_CLK 63 +#define AGILEX5_I3C_1_CORE_CLK 64 +#define AGILEX5_I2C_0_PCLK 65 +#define AGILEX5_I2C_1_PCLK 66 +#define AGILEX5_I2C_EMAC0_PCLK 67 +#define AGILEX5_I2C_EMAC1_PCLK 68 +#define AGILEX5_I2C_EMAC2_PCLK 69 +#define AGILEX5_UART_0_PCLK 70 +#define AGILEX5_UART_1_PCLK 71 +#define AGILEX5_SPTIMER_0_PCLK 72 +#define AGILEX5_SPTIMER_1_PCLK 73 +#define AGILEX5_DFI_CLK 74 +#define AGILEX5_NAND_NF_CLK 75 +#define AGILEX5_NAND_BCH_CLK 76 +#define AGILEX5_SDMMC_SDPHY_REG_CLK 77 +#define AGILEX5_SDMCLK 78 +#define AGILEX5_SOFTPHY_REG_PCLK 79 +#define AGILEX5_SOFTPHY_PHY_CLK 80 +#define AGILEX5_SOFTPHY_CTRL_CLK 81 +#define AGILEX5_NUM_CLKS 82 + +#endif /* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */ --=20 2.25.1 From nobody Sat Feb 7 23:22:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4738EC04A94 for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="372788323" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="372788323" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2023 18:04:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="818587653" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="818587653" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by FMSMGA003.fm.intel.com with ESMTP; 31 Jul 2023 18:04:11 -0700 From: niravkumar.l.rabara@intel.com To: niravkumar.l.rabara@intel.com Cc: adrian.ho.yin.ng@intel.com, andrew@lunn.ch, conor+dt@kernel.org, devicetree@vger.kernel.org, dinguyen@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, netdev@vger.kernel.org, p.zabel@pengutronix.de, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, wen.ping.teh@intel.com Subject: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5 Date: Tue, 1 Aug 2023 09:02:33 +0800 Message-Id: <20230801010234.792557-5-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230801010234.792557-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> <20230801010234.792557-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Add support for Intel's SoCFPGA Agilex5 platform. The clock manager driver for the Agilex5 is very similar to the Agilex platform,we can re-use most of the Agilex clock driver. Signed-off-by: Teh Wen Ping Reviewed-by: Dinh Nguyen Signed-off-by: Niravkumar L Rabara --- drivers/clk/socfpga/clk-agilex.c | 433 ++++++++++++++++++++++++++++++- 1 file changed, 431 insertions(+), 2 deletions(-) diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agi= lex.c index 74d21bd82710..3dcd0f233c17 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2019-2023, Intel Corporation */ #include #include @@ -9,6 +9,7 @@ #include =20 #include +#include =20 #include "stratix10-clk.h" =20 @@ -41,6 +42,67 @@ static const struct clk_parent_data mpu_free_mux[] =3D { .name =3D "f2s-free-clk", }, }; =20 +static const struct clk_parent_data core0_free_mux[] =3D { + { .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", }, + { .fw_name =3D "peri_pll_c0", + .name =3D "peri_pll_c0", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data core1_free_mux[] =3D { + { .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", }, + { .fw_name =3D "peri_pll_c0", + .name =3D "peri_pll_c0", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data core2_free_mux[] =3D { + { .fw_name =3D "main_pll_c0", + .name =3D "main_pll_c0", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data core3_free_mux[] =3D { + { .fw_name =3D "main_pll_c0", + .name =3D "main_pll_c0", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data dsu_free_mux[] =3D { + { .fw_name =3D "main_pll_c2", + .name =3D "main_pll_c2", }, + { .fw_name =3D "peri_pll_c0", + .name =3D "peri_pll_c0", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + static const struct clk_parent_data noc_free_mux[] =3D { { .fw_name =3D "main_pll_c1", .name =3D "main_pll_c1", }, @@ -53,7 +115,6 @@ static const struct clk_parent_data noc_free_mux[] =3D { { .fw_name =3D "f2s-free-clk", .name =3D "f2s-free-clk", }, }; - static const struct clk_parent_data emaca_free_mux[] =3D { { .fw_name =3D "main_pll_c2", .name =3D "main_pll_c2", }, @@ -158,6 +219,110 @@ static const struct clk_parent_data s2f_usr1_free_mux= [] =3D { .name =3D "f2s-free-clk", }, }; =20 +static const struct clk_parent_data agilex5_emaca_free_mux[] =3D { + { .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", }, + { .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data agilex5_emacb_free_mux[] =3D { + { .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", }, + { .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data agilex5_emac_ptp_free_mux[] =3D { + { .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", }, + { .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data agilex5_gpio_db_free_mux[] =3D { + { .fw_name =3D "main_pll_c3", + .name =3D "main_pll_c3", }, + { .fw_name =3D "peri_pll_c1", + .name =3D "peri_pll_c1", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data agilex5_psi_ref_free_mux[] =3D { + { .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", }, + { .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data agilex5_usb31_free_mux[] =3D { + { .fw_name =3D "main_pll_c3", + .name =3D "main_pll_c3", }, + { .fw_name =3D "peri_pll_c2", + .name =3D "peri_pll_c2", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data agilex5_s2f_usr0_free_mux[] =3D { + { .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", }, + { .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + +static const struct clk_parent_data agilex5_s2f_usr1_free_mux[] =3D { + { .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", }, + { .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", }, + { .fw_name =3D "osc1", + .name =3D "osc1", }, + { .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", }, + { .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", }, +}; + static const struct clk_parent_data mpu_mux[] =3D { { .fw_name =3D "mpu_free_clk", .name =3D "mpu_free_clk", }, @@ -165,6 +330,41 @@ static const struct clk_parent_data mpu_mux[] =3D { .name =3D "boot_clk", }, }; =20 +static const struct clk_parent_data core0_mux[] =3D { + { .fw_name =3D "core0_free_clk", + .name =3D "core0_free_clk", }, + { .fw_name =3D "boot_clk", + .name =3D "boot_clk", }, +}; + +static const struct clk_parent_data core1_mux[] =3D { + { .fw_name =3D "core1_free_clk", + .name =3D "core1_free_clk", }, + { .fw_name =3D "boot_clk", + .name =3D "boot_clk", }, +}; + +static const struct clk_parent_data core2_mux[] =3D { + { .fw_name =3D "core2_free_clk", + .name =3D "core2_free_clk", }, + { .fw_name =3D "boot_clk", + .name =3D "boot_clk", }, +}; + +static const struct clk_parent_data core3_mux[] =3D { + { .fw_name =3D "core3_free_clk", + .name =3D "core3_free_clk", }, + { .fw_name =3D "boot_clk", + .name =3D "boot_clk", }, +}; + +static const struct clk_parent_data dsu_mux[] =3D { + { .fw_name =3D "dsu_free_clk", + .name =3D "dsu_free_clk", }, + { .fw_name =3D "boot_clk", + .name =3D "boot_clk", }, +}; + static const struct clk_parent_data emac_mux[] =3D { { .fw_name =3D "emaca_free_clk", .name =3D "emaca_free_clk", }, @@ -223,6 +423,13 @@ static const struct clk_parent_data emac_ptp_mux[] =3D= { .name =3D "boot_clk", }, }; =20 +static const struct clk_parent_data usb31_mux[] =3D { + { .fw_name =3D "usb31_free_clk", + .name =3D "usb31_free_clk", }, + { .fw_name =3D "boot_clk", + .name =3D "boot_clk", }, +}; + /* clocks in AO (always on) controller */ static const struct stratix10_pll_clock agilex_pll_clks[] =3D { { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0, @@ -255,6 +462,25 @@ static const struct stratix10_perip_c_clock agilex_mai= n_perip_c_clks[] =3D { { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC= }, }; =20 +static const struct stratix10_perip_c_clock agilex5_main_perip_c_clks[] = =3D { + { AGILEX5_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, + 0x5C }, + { AGILEX5_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, + 0x60 }, + { AGILEX5_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, + 0x64 }, + { AGILEX5_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, + 0x68 }, + { AGILEX5_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, + 0xB0 }, + { AGILEX5_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, + 0xB4 }, + { AGILEX5_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, + 0xB8 }, + { AGILEX5_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, + 0xBC }, +}; + static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[]= =3D { { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu= _free_mux), 0, 0x3C, 0, 0, 0}, @@ -280,6 +506,46 @@ static const struct stratix10_perip_cnt_clock agilex_m= ain_perip_cnt_clks[] =3D { ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6}, }; =20 +/* Non-SW clock-gated enabled clocks */ +static const struct stratix10_perip_cnt_clock agilex5_main_perip_cnt_clks[= ] =3D { + { AGILEX5_CORE0_FREE_CLK, "core0_free_clk", NULL, core0_free_mux, + ARRAY_SIZE(core0_free_mux), 0, 0x0104, 0, 0, 0 }, + { AGILEX5_CORE1_FREE_CLK, "core1_free_clk", NULL, core1_free_mux, + ARRAY_SIZE(core1_free_mux), 0, 0x0104, 0, 0, 0 }, + { AGILEX5_CORE2_FREE_CLK, "core2_free_clk", NULL, core2_free_mux, + ARRAY_SIZE(core2_free_mux), 0, 0x010C, 0, 0, 0 }, + { AGILEX5_CORE3_FREE_CLK, "core3_free_clk", NULL, core3_free_mux, + ARRAY_SIZE(core3_free_mux), 0, 0x0110, 0, 0, 0 }, + { AGILEX5_DSU_FREE_CLK, "dsu_free_clk", NULL, dsu_free_mux, + ARRAY_SIZE(dsu_free_mux), 0, 0x0100, 0, 0, 0 }, + { AGILEX5_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, + ARRAY_SIZE(noc_free_mux), 0, 0x40, 0, 0, 0 }, + { AGILEX5_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, + agilex5_emaca_free_mux, ARRAY_SIZE(agilex5_emaca_free_mux), 0, 0xD4, + 0, 0x88, 0 }, + { AGILEX5_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, + agilex5_emacb_free_mux, ARRAY_SIZE(agilex5_emacb_free_mux), 0, 0xD8, + 0, 0x88, 1 }, + { AGILEX5_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, + agilex5_emac_ptp_free_mux, ARRAY_SIZE(agilex5_emac_ptp_free_mux), 0, + 0xDC, 0, 0x88, 2 }, + { AGILEX5_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, + agilex5_gpio_db_free_mux, ARRAY_SIZE(agilex5_gpio_db_free_mux), 0, + 0xE0, 0, 0x88, 3 }, + { AGILEX5_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, + agilex5_s2f_usr0_free_mux, ARRAY_SIZE(agilex5_s2f_usr0_free_mux), 0, + 0xE8, 0, 0x30, 2 }, + { AGILEX5_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, + agilex5_s2f_usr1_free_mux, ARRAY_SIZE(agilex5_s2f_usr1_free_mux), 0, + 0xEC, 0, 0x88, 5 }, + { AGILEX5_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, + agilex5_psi_ref_free_mux, ARRAY_SIZE(agilex5_psi_ref_free_mux), 0, + 0xF0, 0, 0x88, 6 }, + { AGILEX5_USB31_FREE_CLK, "usb31_free_clk", NULL, + agilex5_usb31_free_mux, ARRAY_SIZE(agilex5_usb31_free_mux), 0, 0xF8, + 0, 0x88, 7 }, +}; + static const struct stratix10_gate_clock agilex_gate_clks[] =3D { { AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24, 0, 0, 0, 0, 0x30, 0, 0}, @@ -335,6 +601,122 @@ static const struct stratix10_gate_clock agilex_gate_= clks[] =3D { 10, 0, 0, 0, 0, 0, 4}, }; =20 +/* SW Clock gate enabled clocks */ +static const struct stratix10_gate_clock agilex5_gate_clks[] =3D { + /* Main PLL0 Begin */ + /* MPU clocks */ + { AGILEX5_CORE0_CLK, "core0_clk", NULL, core0_mux, + ARRAY_SIZE(core0_mux), 0, 0x24, 8, 0, 0, 0, 0x30, 5, 0 }, + { AGILEX5_CORE1_CLK, "core1_clk", NULL, core1_mux, + ARRAY_SIZE(core1_mux), 0, 0x24, 9, 0, 0, 0, 0x30, 5, 0 }, + { AGILEX5_CORE2_CLK, "core2_clk", NULL, core2_mux, + ARRAY_SIZE(core2_mux), 0, 0x24, 10, 0, 0, 0, 0x30, 6, 0 }, + { AGILEX5_CORE3_CLK, "core3_clk", NULL, core3_mux, + ARRAY_SIZE(core3_mux), 0, 0x24, 11, 0, 0, 0, 0x30, 7, 0 }, + { AGILEX5_MPU_CLK, "dsu_clk", NULL, dsu_mux, ARRAY_SIZE(dsu_mux), 0, 0, + 0, 0, 0, 0, 0x34, 4, 0 }, + { AGILEX5_MPU_PERIPH_CLK, "mpu_periph_clk", NULL, dsu_mux, + ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 20, 2, 0x34, 4, 0 }, + { AGILEX5_MPU_CCU_CLK, "mpu_ccu_clk", NULL, dsu_mux, + ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 18, 2, 0x34, 4, 0 }, + { AGILEX5_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, + ARRAY_SIZE(noc_mux), 0, 0x24, 1, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, + 0x24, 2, 0x44, 4, 2, 0x30, 1, 0 }, + { AGILEX5_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, + ARRAY_SIZE(noc_mux), 0, 0, 0, 0x44, 2, 2, 0x30, 1, 0 }, + { AGILEX5_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), + CLK_IS_CRITICAL, 0x24, 3, 0x44, 6, 2, 0x30, 1, 0 }, + + /* Core sight clocks*/ + { AGILEX5_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, + 0x24, 4, 0x44, 24, 2, 0x30, 1, 0 }, + { AGILEX5_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, + ARRAY_SIZE(noc_mux), 0, 0x24, 4, 0x44, 26, 2, 0x30, 1, 0 }, + { AGILEX5_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, 4, + 0x44, 28, 1, 0, 0, 0 }, + /* Main PLL0 End */ + + /* Main Peripheral PLL1 Begin */ + { AGILEX5_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), + 0, 0x7C, 0, 0, 0, 0, 0x94, 26, 0 }, + { AGILEX5_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), + 0, 0x7C, 1, 0, 0, 0, 0x94, 27, 0 }, + { AGILEX5_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), + 0, 0x7C, 2, 0, 0, 0, 0x94, 28, 0 }, + { AGILEX5_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, + ARRAY_SIZE(emac_ptp_mux), 0, 0x7C, 3, 0, 0, 0, 0x88, 2, 0 }, + { AGILEX5_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, + ARRAY_SIZE(gpio_db_mux), 0, 0x7C, 4, 0x98, 0, 16, 0x88, 3, 1 }, + /* Main Peripheral PLL1 End */ + + /* Peripheral clocks */ + { AGILEX5_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, + ARRAY_SIZE(s2f_user0_mux), 0, 0x24, 6, 0, 0, 0, 0x30, 2, 0 }, + { AGILEX5_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, + ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0 }, + { AGILEX5_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, + ARRAY_SIZE(psi_mux), 0, 0x7C, 7, 0, 0, 0, 0x88, 6, 0 }, + { AGILEX5_USB31_SUSPEND_CLK, "usb31_suspend_clk", NULL, usb31_mux, + ARRAY_SIZE(usb31_mux), 0, 0x7C, 25, 0, 0, 0, 0x88, 7, 0 }, + { AGILEX5_USB31_BUS_CLK_EARLY, "usb31_bus_clk_early", "l4_main_clk", + NULL, 1, 0, 0x7C, 25, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_USB2OTG_HCLK, "usb2otg_hclk", "l4_mp_clk", NULL, 1, 0, 0x7C, + 8, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPIM_0_CLK, "spim_0_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 9, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPIM_1_CLK, "spim_1_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 11, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPIS_0_CLK, "spis_0_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 12, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPIS_1_CLK, "spis_1_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 13, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_DMA_CORE_CLK, "dma_core_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, + 14, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_DMA_HS_CLK, "dma_hs_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 14, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I3C_0_CORE_CLK, "i3c_0_core_clk", "l4_mp_clk", NULL, 1, 0, + 0x7C, 18, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I3C_1_CORE_CLK, "i3c_1_core_clk", "l4_mp_clk", NULL, 1, 0, + 0x7C, 19, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_0_PCLK, "i2c_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 15, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_1_PCLK, "i2c_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 16, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_EMAC0_PCLK, "i2c_emac0_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 17, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_EMAC1_PCLK, "i2c_emac1_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 22, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_EMAC2_PCLK, "i2c_emac2_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 27, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_UART_0_PCLK, "uart_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 20, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_UART_1_PCLK, "uart_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 21, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPTIMER_0_PCLK, "sptimer_0_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 23, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPTIMER_1_PCLK, "sptimer_1_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 24, 0, 0, 0, 0, 0, 0 }, + + /* NAND, SD/MMC and SoftPHY overall clocking */ + { AGILEX5_DFI_CLK, "dfi_clk", "l4_mp_clk", NULL, 1, 0, 0, 0, 0x44, 16, + 2, 0, 0, 0 }, + { AGILEX5_NAND_NF_CLK, "nand_nf_clk", "dfi_clk", NULL, 1, 0, 0x7C, 10, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_NAND_BCH_CLK, "nand_bch_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, + 10, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SDMMC_SDPHY_REG_CLK, "sdmmc_sdphy_reg_clk", "l4_mp_clk", NULL, + 1, 0, 0x7C, 5, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SDMCLK, "sdmclk", "dfi_clk", NULL, 1, 0, 0x7C, 5, 0, 0, 0, 0, + 0, 0 }, + { AGILEX5_SOFTPHY_REG_PCLK, "softphy_reg_pclk", "l4_mp_clk", NULL, 1, 0, + 0x7C, 26, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SOFTPHY_PHY_CLK, "softphy_phy_clk", "l4_mp_clk", NULL, 1, 0, + 0x7C, 26, 0x44, 16, 2, 0, 0, 0 }, + { AGILEX5_SOFTPHY_CTRL_CLK, "softphy_ctrl_clk", "dfi_clk", NULL, 1, 0, + 0x7C, 26, 0, 0, 0, 0, 0, 0 }, +}; + static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks, int nums, struct stratix10_clock_data *data) { @@ -535,6 +917,51 @@ static int n5x_clkmgr_init(struct platform_device *pde= v) return 0; } =20 +static int agilex5_clkmgr_init(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct stratix10_clock_data *clk_data; + struct resource *res; + void __iomem *base; + int i, num_clks; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + num_clks =3D AGILEX5_NUM_CLKS; + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, clk_data.hws, + num_clks), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + for (i =3D 0; i < num_clks; i++) + clk_data->clk_data.hws[i] =3D ERR_PTR(-ENOENT); + + clk_data->base =3D base; + clk_data->clk_data.num =3D num_clks; + + agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), + clk_data); + + agilex_clk_register_c_perip(agilex5_main_perip_c_clks, + ARRAY_SIZE(agilex5_main_perip_c_clks), + clk_data); + + agilex_clk_register_cnt_perip(agilex5_main_perip_cnt_clks, + ARRAY_SIZE(agilex5_main_perip_cnt_clks), + clk_data); + + agilex_clk_register_gate(agilex5_gate_clks, + ARRAY_SIZE(agilex5_gate_clks), clk_data); + + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data); + return 0; +} + static int agilex_clkmgr_probe(struct platform_device *pdev) { int (*probe_func)(struct platform_device *init_func); @@ -550,6 +977,8 @@ static const struct of_device_id agilex_clkmgr_match_ta= ble[] =3D { .data =3D agilex_clkmgr_init }, { .compatible =3D "intel,easic-n5x-clkmgr", .data =3D n5x_clkmgr_init }, + { .compatible =3D "intel,agilex5-clkmgr", + .data =3D agilex5_clkmgr_init }, { } }; =20 --=20 2.25.1 From nobody Sat Feb 7 23:22:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15B6BC04E69 for ; Tue, 1 Aug 2023 01:06:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230146AbjHABGp (ORCPT ); Mon, 31 Jul 2023 21:06:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231628AbjHABGm (ORCPT ); Mon, 31 Jul 2023 21:06:42 -0400 Received: from mgamail.intel.com (unknown [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AF901FFD; Mon, 31 Jul 2023 18:06:24 -0700 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X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="818587732" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by FMSMGA003.fm.intel.com with ESMTP; 31 Jul 2023 18:04:16 -0700 From: niravkumar.l.rabara@intel.com To: niravkumar.l.rabara@intel.com Cc: adrian.ho.yin.ng@intel.com, andrew@lunn.ch, conor+dt@kernel.org, devicetree@vger.kernel.org, dinguyen@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, netdev@vger.kernel.org, p.zabel@pengutronix.de, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, wen.ping.teh@intel.com Subject: [PATCH v2 5/5] arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA Date: Tue, 1 Aug 2023 09:02:34 +0800 Message-Id: <20230801010234.792557-6-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230801010234.792557-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> <20230801010234.792557-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Add the initial device tree files for Intel Agilex5 SoCFPGA platform. Reviewed-by: Dinh Nguyen Signed-off-by: Niravkumar L Rabara --- arch/arm64/boot/dts/intel/Makefile | 1 + .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 468 ++++++++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 39 ++ 3 files changed, 508 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel= /Makefile index c2a723838344..d39cfb723f5b 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,5 +2,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ + socfpga_agilex5_socdk.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) +=3D keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/bo= ot/dts/intel/socfpga_agilex5.dtsi new file mode 100644 index 000000000000..dcdaf7064953 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Intel Corporation + */ + +/dts-v1/; +#include +#include +#include +#include +#include + +/ { + compatible =3D "intel,socfpga-agilex5"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x80000000 0x0 0x2000000>; + alignment =3D <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a76"; + reg =3D <0x200>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a76"; + reg =3D <0x300>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + intc: interrupt-controller@1d000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x1d000000 0 0x10000>, + <0x0 0x1d060000 0 0x100000>; + ranges; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D<2>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + + its: msi-controller@1d040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x1d040000 0x0 0x20000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + /* Clock tree 5 main sources*/ + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + }; + + osc1: osc1 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + }; + + qspi_clk: qspi-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <200000000>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&intc>; + interrupts =3D , + , + , + ; + }; + + usbphy0: usbphy { + #phy-cells =3D <0>; + compatible =3D "usb-nop-xceiv"; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0xffffffff>; + #address-cells =3D <1>; + #size-cells =3D <1>; + device_type =3D "soc"; + interrupt-parent =3D <&intc>; + + clkmgr: clock-controller@10d10000 { + compatible =3D "intel,agilex5-clkmgr"; + reg =3D <0x10d10000 0x1000>; + #clock-cells =3D <1>; + }; + + i2c0: i2c@10c02800 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02800 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + resets =3D <&rst I2C0_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c1: i2c@10c02900 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02900 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + resets =3D <&rst I2C1_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c2: i2c@10c02a00 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02a00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + resets =3D <&rst I2C2_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c3: i2c@10c02b00 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02b00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + resets =3D <&rst I2C3_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c4: i2c@10c02c00 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02c00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + resets =3D <&rst I2C4_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i3c0: i3c-master@10da0000 { + compatible =3D "snps,dw-i3c-master-1.00a"; + reg =3D <0x10da0000 0x1000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&clkmgr AGILEX5_L4_MP_CLK>; + status =3D "disabled"; + }; + + i3c1: i3c-master@10da1000 { + compatible =3D "snps,dw-i3c-master-1.00a"; + reg =3D <0x10da1000 0x1000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&clkmgr AGILEX5_L4_MP_CLK>; + status =3D "disabled"; + }; + + gpio1: gpio@10c03300 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x10c03300 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + resets =3D <&rst GPIO1_RESET>; + status =3D "disabled"; + + portb: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <24>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + }; + }; + + nand: nand-controller@10b80000 { + compatible =3D "cdns,hp-nfc"; + reg =3D <0x10b80000 0x10000>, + <0x10840000 0x10000>; + reg-names =3D "reg", "sdma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&clkmgr AGILEX5_NAND_NF_CLK>; + cdns,board-delay-ps =3D <4830>; + status =3D "disabled"; + }; + + ocram: sram@0 { + compatible =3D "mmio-sram"; + reg =3D <0x00000000 0x80000>; + ranges =3D <0 0 0x80000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + dmac0: dma-controller@10db0000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0x10db0000 0x500>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names =3D "core-clk", "cfgr-clk"; + interrupt-parent =3D <&intc>; + interrupts =3D ; + #dma-cells =3D <1>; + dma-channels =3D <4>; + snps,dma-masters =3D <1>; + snps,data-width =3D <2>; + snps,block-size =3D <32767 32767 32767 32767>; + snps,priority =3D <0 1 2 3>; + snps,axi-max-burst-len =3D <8>; + }; + + dmac1: dma-controller@10dc0000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0x10dc0000 0x500>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names =3D "core-clk", "cfgr-clk"; + interrupt-parent =3D <&intc>; + interrupts =3D ; + #dma-cells =3D <1>; + dma-channels =3D <4>; + snps,dma-masters =3D <1>; + snps,data-width =3D <2>; + snps,block-size =3D <32767 32767 32767 32767>; + snps,priority =3D <0 1 2 3>; + snps,axi-max-burst-len =3D <8>; + }; + + rst: rstmgr@10d11000 { + compatible =3D "altr,stratix10-rst-mgr", "altr,rst-mgr"; + reg =3D <0x10d11000 0x1000>; + #reset-cells =3D <1>; + }; + + spi0: spi@10da4000 { + compatible =3D "snps,dw-apb-ssi"; + reg =3D <0x10da4000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + resets =3D <&rst SPIM0_RESET>; + reset-names =3D "spi"; + reg-io-width =3D <4>; + num-cs =3D <4>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>; + dmas =3D <&dmac0 2>, <&dmac0 3>; + dma-names =3D"tx", "rx"; + status =3D "disabled"; + + }; + + spi1: spi@10da5000 { + compatible =3D "snps,dw-apb-ssi"; + reg =3D <0x10da5000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + resets =3D <&rst SPIM1_RESET>; + reset-names =3D "spi"; + reg-io-width =3D <4>; + num-cs =3D <4>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>; + status =3D "disabled"; + }; + + sysmgr: sysmgr@10d12000 { + compatible =3D "altr,sys-mgr-s10","altr,sys-mgr"; + reg =3D <0x10d12000 0x500>; + }; + + timer0: timer0@10c03000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0x10c03000 0x100>; + interrupts =3D ; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + timer1: timer1@10c03100 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0x10c03100 0x100>; + interrupts =3D ; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + timer2: timer2@10d00000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0x10d00000 0x100>; + interrupts =3D ; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + timer3: timer3@10d00100 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0x10d00100 0x100>; + interrupts =3D ; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + uart0: serial@10c02000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x10c02000 0x100>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + resets =3D <&rst UART0_RESET>; + status =3D "disabled"; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + uart1: serial@10c02100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x10c02100 0x100>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + resets =3D <&rst UART1_RESET>; + status =3D "disabled"; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + usb0: usb@10b00000 { + compatible =3D "snps,dwc2"; + reg =3D <0x10b00000 0x40000>; + interrupts =3D ; + phys =3D <&usbphy0>; + phy-names =3D "usb2-phy"; + resets =3D <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names =3D "dwc2", "dwc2-ecc"; + clocks =3D <&clkmgr AGILEX5_USB2OTG_HCLK>; + clock-names =3D "otg"; + status =3D "disabled"; + }; + + watchdog0: watchdog@10d00200 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00200 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG0_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog1: watchdog@10d00300 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00300 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG1_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog2: watchdog@10d00400 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00400 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG2_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog3: watchdog@10d00500 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00500 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG3_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog4: watchdog@10d00600 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00600 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG4_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + qspi: spi@108d2000 { + compatible =3D "intel,socfpga-qspi", "cdns,qspi-nor"; + reg =3D <0x108d2000 0x100>, + <0x10900000 0x100000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + cdns,fifo-depth =3D <128>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x00000000>; + clocks =3D <&qspi_clk>; + status =3D "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm= 64/boot/dts/intel/socfpga_agilex5_socdk.dts new file mode 100644 index 000000000000..c533e5a3a610 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model =3D "SoCFPGA Agilex5 SoCDK"; + compatible =3D "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&gpio1 { + status =3D "okay"; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&usb0 { + status =3D "okay"; + disable-over-current; +}; + +&watchdog0 { + status =3D "okay"; +}; --=20 2.25.1