[PATCH v2 0/2] x86/cacheinfo: Set the number of leaves per CPU

Ricardo Neri posted 2 patches 2 years, 7 months ago
There is a newer version of this series
arch/x86/kernel/cpu/cacheinfo.c | 50 ++++++++++++++++-----------------
1 file changed, 25 insertions(+), 25 deletions(-)
[PATCH v2 0/2] x86/cacheinfo: Set the number of leaves per CPU
Posted by Ricardo Neri 2 years, 7 months ago
Hi,

This v2 of now a patchset to set the number of cache leaves independently
for each CPU. v1 can be found here [1].

These are the changes since v2:
  * Dave Hansen, suggested to use the existing per-CPU ci_cpu_cacheinfo
    variable. Now the global variable num_cache_leaves became useless.
  * While here, I noticed that init_cache_level() also became useless:
    x86 does not need ci_cpu_cacheinfo::num_levels.

These patches apply cleanly on top of the master branch of the tip tree.

Thanks and BR,
Ricardo


[1]. https://lore.kernel.org/lkml/20230314231658.30169-1-ricardo.neri-calderon@linux.intel.com/


Ricardo Neri (2):
  x86/cacheinfo: Delete global num_cache_leaves
  x86/cacheinfo: Clean out init_cache_level()

 arch/x86/kernel/cpu/cacheinfo.c | 50 ++++++++++++++++-----------------
 1 file changed, 25 insertions(+), 25 deletions(-)

-- 
2.25.1
Re: [PATCH v2 0/2] x86/cacheinfo: Set the number of leaves per CPU
Posted by Ricardo Neri 2 years, 7 months ago
On Sun, Apr 23, 2023 at 05:19:54PM -0700, Ricardo Neri wrote:
> Hi,
> 
> This v2 of now a patchset to set the number of cache leaves independently
> for each CPU. v1 can be found here [1].
> 
> These are the changes since v2:
>   * Dave Hansen, suggested to use the existing per-CPU ci_cpu_cacheinfo
>     variable. Now the global variable num_cache_leaves became useless.
>   * While here, I noticed that init_cache_level() also became useless:
>     x86 does not need ci_cpu_cacheinfo::num_levels.
> 
> These patches apply cleanly on top of the master branch of the tip tree.

FYI, I see a NULL pointer dereference when I apply this patchset on top of
v6.4-rc1. I started a discussion here[1].

[1]. https://lore.kernel.org/all/20230510191207.GA18514@ranerica-svr.sc.intel.com/