From nobody Tue Dec 16 18:22:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C473EC6FD18 for ; Mon, 24 Apr 2023 00:18:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230186AbjDXARQ (ORCPT ); Sun, 23 Apr 2023 20:17:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230139AbjDXARN (ORCPT ); Sun, 23 Apr 2023 20:17:13 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EF5794; Sun, 23 Apr 2023 17:17:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682295431; x=1713831431; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=/FwfvdilZ1y10bo98zmMqAo6SyCOKge7Mha+KtjYw10=; b=efj7+MvYs8mNmk8TnDqGoX16aGEb2r9ec48ZpXzPZrMA1NH+9ULC6vKf j/ziF6/ebpd2t9iIAPyVBmQDJmOAoiGXQEH3dj1IfJbca4ZMS2jzu4mmq u8KUkpyK8E0WMHxirRPX5mR+tg6ZVSbJCqlEvUyOgoyQ8xJ+h6oA2QyFo TZnYGzWQWqjfetGOrec6GdqSaPFR6eq45W1doij7U+djHQEGwpghfOjNJ kS0F7cXzr+4Je+TOkE4pVDIi/UBgxnSVSn8wVMOIB9jfzM/On5cSeIGeh tNLJx3eDJ4rnuEbb40Na0Cs0V6RMPzClzCS5LSg5fcGU/NSA11DY4S4cE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="411605278" X-IronPort-AV: E=Sophos;i="5.99,221,1677571200"; d="scan'208";a="411605278" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2023 17:17:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="1022502122" X-IronPort-AV: E=Sophos;i="5.99,221,1677571200"; d="scan'208";a="1022502122" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga005.fm.intel.com with ESMTP; 23 Apr 2023 17:17:09 -0700 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Chen Yu , Len Brown , Pu Wen , "Rafael J. Wysocki" , Srinivas Pandruvada , Zhang Rui , Ricardo Neri , linux-kernel@vger.kernel.org, Ricardo Neri , stable@vger.kernel.org Subject: [PATCH v2 1/2] x86/cacheinfo: Delete global num_cache_leaves Date: Sun, 23 Apr 2023 17:19:55 -0700 Message-Id: <20230424001956.21434-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230424001956.21434-1-ricardo.neri-calderon@linux.intel.com> References: <20230424001956.21434-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Linux remembers cpu_cachinfo::num_leaves per CPU, but x86 initializes all CPUs from the same global "num_cache_leaves". This is erroneous on systems like Meteor Lake, which has different num_leaves per CPU. Delete the global "num_cache_leaves" and initialize num_leaves accurately on each CPU. Cc: Andreas Herrmann Cc: Chen Yu Cc: Len Brown Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Srinivas Pandruvada Cc: Zhang Rui Cc: stable@vger.kernel.org Reviewed-by: Len Brown Signed-off-by: Ricardo Neri --- After this change, all CPUs will traverse CPUID leaf 0x4 when booted for the first time. On systems with asymmetric cache topologies this is useless work. Creating a list of processor models that have asymmetric cache topologies was considered. The burden of maintaining such list would outweigh the performance benefit of skipping this extra step. --- Changes since v1: * Do not make num_cache_leaves a per-CPU variable. Instead, reuse the existing per-CPU ci_cpu_cacheinfo variable. (Dave Hansen) --- arch/x86/kernel/cpu/cacheinfo.c | 45 ++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 4063e8991211..45c4e9daf3f1 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -176,7 +176,16 @@ struct _cpuid4_info_regs { struct amd_northbridge *nb; }; =20 -static unsigned short num_cache_leaves; +static inline unsigned int get_num_cache_leaves(unsigned int cpu) +{ + return get_cpu_cacheinfo(cpu)->num_leaves; +} + +static inline void +set_num_cache_leaves(unsigned int nr_leaves, unsigned int cpu) +{ + get_cpu_cacheinfo(cpu)->num_leaves =3D nr_leaves; +} =20 /* AMD doesn't have CPUID4. Emulate it here to report the same information to the user. This makes some assumptions about the machine: @@ -716,19 +725,21 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *= c, int cpu) void init_amd_cacheinfo(struct cpuinfo_x86 *c) { =20 + unsigned int cpu =3D c->cpu_index; + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - num_cache_leaves =3D find_num_cache_leaves(c); + set_num_cache_leaves(find_num_cache_leaves(c), cpu); } else if (c->extended_cpuid_level >=3D 0x80000006) { if (cpuid_edx(0x80000006) & 0xf000) - num_cache_leaves =3D 4; + set_num_cache_leaves(4, cpu); else - num_cache_leaves =3D 3; + set_num_cache_leaves(3, cpu); } } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { - num_cache_leaves =3D find_num_cache_leaves(c); + set_num_cache_leaves(find_num_cache_leaves(c), c->cpu_index); } =20 void init_intel_cacheinfo(struct cpuinfo_x86 *c) @@ -738,24 +749,21 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) unsigned int new_l1d =3D 0, new_l1i =3D 0; /* Cache sizes from cpuid(4) */ unsigned int new_l2 =3D 0, new_l3 =3D 0, i; /* Cache sizes from cpuid(4) = */ unsigned int l2_id =3D 0, l3_id =3D 0, num_threads_sharing, index_msb; -#ifdef CONFIG_SMP unsigned int cpu =3D c->cpu_index; -#endif =20 if (c->cpuid_level > 3) { - static int is_initialized; - - if (is_initialized =3D=3D 0) { - /* Init num_cache_leaves from boot CPU */ - num_cache_leaves =3D find_num_cache_leaves(c); - is_initialized++; - } + /* + * There should be at least one leaf. A non-zero value means + * that the number of leaves has been initialized. + */ + if (!get_num_cache_leaves(cpu)) + set_num_cache_leaves(find_num_cache_leaves(c), cpu); =20 /* * Whenever possible use cpuid(4), deterministic cache * parameters cpuid leaf to find the cache details */ - for (i =3D 0; i < num_cache_leaves; i++) { + for (i =3D 0; i < get_num_cache_leaves(cpu); i++) { struct _cpuid4_info_regs this_leaf =3D {}; int retval; =20 @@ -791,14 +799,14 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for * trace cache */ - if ((num_cache_leaves =3D=3D 0 || c->x86 =3D=3D 15) && c->cpuid_level > 1= ) { + if ((!get_num_cache_leaves(cpu) || c->x86 =3D=3D 15) && c->cpuid_level > = 1) { /* supports eax=3D2 call */ int j, n; unsigned int regs[4]; unsigned char *dp =3D (unsigned char *)regs; int only_trace =3D 0; =20 - if (num_cache_leaves !=3D 0 && c->x86 =3D=3D 15) + if (get_num_cache_leaves(cpu) && c->x86 =3D=3D 15) only_trace =3D 1; =20 /* Number of times to iterate */ @@ -1000,12 +1008,9 @@ int init_cache_level(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); =20 - if (!num_cache_leaves) - return -ENOENT; if (!this_cpu_ci) return -EINVAL; this_cpu_ci->num_levels =3D 3; - this_cpu_ci->num_leaves =3D num_cache_leaves; return 0; } =20 --=20 2.25.1 From nobody Tue Dec 16 18:22:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3714C77B60 for ; Mon, 24 Apr 2023 00:18:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230134AbjDXART (ORCPT ); Sun, 23 Apr 2023 20:17:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230121AbjDXARN (ORCPT ); Sun, 23 Apr 2023 20:17:13 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D771BAA for ; Sun, 23 Apr 2023 17:17:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682295431; x=1713831431; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=zQzAyc+oLBHOEgweof17wjj2fy/1ScIcJB+YP8+nzTQ=; b=anVtz89ImrfgENVeGigQhcMz6rSIzR4jpNADDbxqZLejj3O+/vnU0o8U KY+G0jcPEWddi75widwYTcCLrPF4RfPS8WniW6blUzFeEqb/U2Yy7sk4M c56w9TE9RAmk/LP7tYoEhTVG4LgCYOsdTVzhKcFwh/7LjWrMZp2k84INW gXWvLG4aErsCbjPaeTfCdotKz3kGxpuBXgHz7V0Ge/ckfNuYr6anL+miD onldWkRQ89sGxKxXNui5PutWIkNsFJMV9yZpleEFgQ8ZaEwjSkcDxdIoS 6vNrmDzAmsFzp1Ry5/0qdLIo4qflfAFVWxnpxcx+TpJIOXwlpggRtXJR2 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="411605283" X-IronPort-AV: E=Sophos;i="5.99,221,1677571200"; d="scan'208";a="411605283" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2023 17:17:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="1022502126" X-IronPort-AV: E=Sophos;i="5.99,221,1677571200"; d="scan'208";a="1022502126" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga005.fm.intel.com with ESMTP; 23 Apr 2023 17:17:10 -0700 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Chen Yu , Len Brown , Pu Wen , "Rafael J. Wysocki" , Srinivas Pandruvada , Zhang Rui , Ricardo Neri , linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v2 2/2] x86/cacheinfo: Clean out init_cache_level() Date: Sun, 23 Apr 2023 17:19:56 -0700 Message-Id: <20230424001956.21434-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230424001956.21434-1-ricardo.neri-calderon@linux.intel.com> References: <20230424001956.21434-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" init_cache_level() no longer has a purpose on x86. It no longer needs to set num_leaves, and it never had to set num_levels, which was unnecessary on x86. Replace it with "return 0" simply to override the weak function, which would return an error. Cc: Andreas Herrmann Cc: Chen Yu Cc: Len Brown Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Srinivas Pandruvada Cc: Zhang Rui Reviewed-by: Len Brown Signed-off-by: Ricardo Neri --- Changes since v1: * Introduced this patch. --- arch/x86/kernel/cpu/cacheinfo.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 45c4e9daf3f1..454247e459b1 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -1006,11 +1006,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, =20 int init_cache_level(unsigned int cpu) { - struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); - - if (!this_cpu_ci) - return -EINVAL; - this_cpu_ci->num_levels =3D 3; return 0; } =20 --=20 2.25.1