From: Aswath Govindraju <a-govindraju@ti.com>
Add support for two instance of OSPI in J721S2 SoC.
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
---
Changes from v13:
* No changes. Only rebased on top of linux-next
Changes from v12:
* Disabled only nodes that need additional info
Changes from v11:
* Cleaned up comments
Changes from v10:
* Documented the reason for disabling the nodes by default.
* Removed Link tag from commmit message
Changes from v9:
* Disabled fss, ospi nodes by default in common DT file
Changes from v8:
* Updated "ranges" property to fix dtbs warnings
Changes from v7:
* Removed "reg" property from syscon node
* Renamed the "syscon" node to "bus" to after change in
compatible property
Changes from v6:
* Fixed the syscon node's compatible property
Changes from v5:
* Updated the syscon node's compatible property
* Removed Cc tags from commit message
Changes from v4:
* No change
Changes from v3:
* No change
Changes from v2:
* No change
Changes from v1:
* No change
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index a353705a7463..6e981fe4727e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -379,4 +379,48 @@
compatible = "ti,am3359-adc";
};
};
+
+ fss: bus@47000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47040000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 109 5>;
+ assigned-clocks = <&k3_clks 109 5>;
+ assigned-clock-parents = <&k3_clks 109 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* Needs pinmux */
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47050000 0x00 0x100>,
+ <0x07 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 110 5>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* Needs pinmux */
+ };
+ };
};
--
2.17.1
Hi, On 31/03/2023 12:00, Ravi Gunasekaran wrote: > From: Aswath Govindraju <a-govindraju@ti.com> > > Add support for two instance of OSPI in J721S2 SoC. > > Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> > Signed-off-by: Matt Ranostay <mranostay@ti.com> > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> > --- > Changes from v13: > * No changes. Only rebased on top of linux-next > > Changes from v12: > * Disabled only nodes that need additional info > > Changes from v11: > * Cleaned up comments > > Changes from v10: > * Documented the reason for disabling the nodes by default. > * Removed Link tag from commmit message > > Changes from v9: > * Disabled fss, ospi nodes by default in common DT file > > Changes from v8: > * Updated "ranges" property to fix dtbs warnings > > Changes from v7: > * Removed "reg" property from syscon node > * Renamed the "syscon" node to "bus" to after change in > compatible property > > Changes from v6: > * Fixed the syscon node's compatible property > > Changes from v5: > * Updated the syscon node's compatible property > * Removed Cc tags from commit message > > Changes from v4: > * No change > > Changes from v3: > * No change > > Changes from v2: > * No change > > Changes from v1: > * No change > > .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 44 +++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > index a353705a7463..6e981fe4727e 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > @@ -379,4 +379,48 @@ > compatible = "ti,am3359-adc"; > }; > }; > + > + fss: bus@47000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, > + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, > + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; > + > + ospi0: spi@47040000 { > + compatible = "ti,am654-ospi", "cdns,qspi-nor"; > + reg = <0x00 0x47040000 0x00 0x100>, > + <0x05 0x00000000 0x01 0x00000000>; > + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; > + cdns,fifo-depth = <256>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x0>; > + clocks = <&k3_clks 109 5>; > + assigned-clocks = <&k3_clks 109 5>; > + assigned-clock-parents = <&k3_clks 109 7>; > + assigned-clock-rates = <166666666>; > + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; /* Needs pinmux */ > + }; > + > + ospi1: spi@47050000 { > + compatible = "ti,am654-ospi", "cdns,qspi-nor"; > + reg = <0x00 0x47050000 0x00 0x100>, > + <0x07 0x00000000 0x01 0x00000000>; > + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; > + cdns,fifo-depth = <256>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x0>; > + clocks = <&k3_clks 110 5>; What about clock parent and clock rate assignment like it was done for osip0? > + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; /* Needs pinmux */ > + }; > + }; > }; cheers, -roger
Roger, On 4/25/2023 5:02 PM, Roger Quadros wrote: > Hi, > > On 31/03/2023 12:00, Ravi Gunasekaran wrote: >> From: Aswath Govindraju <a-govindraju@ti.com> >> >> Add support for two instance of OSPI in J721S2 SoC. >> >> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> >> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> >> Signed-off-by: Matt Ranostay <mranostay@ti.com> >> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> >> --- [...] >> + clocks = <&k3_clks 109 5>; >> + assigned-clocks = <&k3_clks 109 5>; >> + assigned-clock-parents = <&k3_clks 109 7>; >> + assigned-clock-rates = <166666666>; >> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; /* Needs pinmux */ >> + }; >> + >> + ospi1: spi@47050000 { >> + compatible = "ti,am654-ospi", "cdns,qspi-nor"; >> + reg = <0x00 0x47050000 0x00 0x100>, >> + <0x07 0x00000000 0x01 0x00000000>; >> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; >> + cdns,fifo-depth = <256>; >> + cdns,fifo-width = <4>; >> + cdns,trigger-address = <0x0>; >> + clocks = <&k3_clks 110 5>; > What about clock parent and clock rate assignment like it was done for osip0? ospi1 uses default values. >> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; /* Needs pinmux */ >> + }; >> + }; >> }; > cheers, > -roger
© 2016 - 2025 Red Hat, Inc.