From nobody Tue Sep 9 16:54:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA04FC76196 for ; Fri, 31 Mar 2023 09:01:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231684AbjCaJBQ (ORCPT ); Fri, 31 Mar 2023 05:01:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231851AbjCaJA4 (ORCPT ); Fri, 31 Mar 2023 05:00:56 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C04027DB3; Fri, 31 Mar 2023 02:00:53 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32V90iNL110890; Fri, 31 Mar 2023 04:00:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680253244; bh=aHs88x0K+Dx6jUkvzGmVZsklNMBBu8IcZc2WLjXqmQ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fgljAcJFbnwNCQ7KC7uOscmqJbIitdoDnWWZHbmjS2tUP8KSdYGIs9YCtz82KzTfC QbJr3m0z7PpEVs2tMRCXL9EgEGxLCXgsxpklwWhOuWLldrOyzIr3lGqLWn44nhrVwb FvLvw9D+g+IqXs3EHPHmN7k0AnGEwvdlQLhEoXMs= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32V90iee036227 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 31 Mar 2023 04:00:44 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 31 Mar 2023 04:00:43 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 31 Mar 2023 04:00:43 -0500 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32V90Sub125579; Fri, 31 Mar 2023 04:00:40 -0500 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v14 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Date: Fri, 31 Mar 2023 14:30:23 +0530 Message-ID: <20230331090028.8373-4-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230331090028.8373-1-r-gunasekaran@ti.com> References: <20230331090028.8373-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add support for two instance of OSPI in J721S2 SoC. Reviewed-by: Vaishnav Achath Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran --- Changes from v13: * No changes. Only rebased on top of linux-next Changes from v12: * Disabled only nodes that need additional info Changes from v11: * Cleaned up comments Changes from v10: * Documented the reason for disabling the nodes by default. * Removed Link tag from commmit message Changes from v9: * Disabled fss, ospi nodes by default in common DT file Changes from v8: * Updated "ranges" property to fix dtbs warnings Changes from v7: * Removed "reg" property from syscon node * Renamed the "syscon" node to "bus" to after change in compatible property Changes from v6: * Fixed the syscon node's compatible property Changes from v5: * Updated the syscon node's compatible property * Removed Cc tags from commit message Changes from v4: * No change Changes from v3: * No change Changes from v2: * No change Changes from v1: * No change .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index a353705a7463..6e981fe4727e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -379,4 +379,48 @@ compatible =3D "ti,am3359-adc"; }; }; + + fss: bus@47000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + ospi0: spi@47040000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 109 5>; + assigned-clocks =3D <&k3_clks 109 5>; + assigned-clock-parents =3D <&k3_clks 109 7>; + assigned-clock-rates =3D <166666666>; + power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; /* Needs pinmux */ + }; + + ospi1: spi@47050000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 110 5>; + power-domains =3D <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; /* Needs pinmux */ + }; + }; }; --=20 2.17.1