Move the generation of the readable APIC regs bitmask to a standalone
helper so that VMX can use the mask for its MSR interception bitmaps.
No functional change intended.
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kvm/lapic.c | 34 +++++++++++++++++++++-------------
arch/x86/kvm/lapic.h | 2 ++
2 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index c49b13418638..19697fe9b2c7 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1529,12 +1529,9 @@ static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
#define APIC_REGS_MASK(first, count) \
(APIC_REG_MASK(first) * ((1ull << (count)) - 1))
-static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
- void *data)
+u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic)
{
- unsigned char alignment = offset & 0xf;
- u32 result;
- /* this bitmask has a bit cleared for each reserved register */
+ /* Leave bits '0' for reserved and write-only registers. */
u64 valid_reg_mask =
APIC_REG_MASK(APIC_ID) |
APIC_REG_MASK(APIC_LVR) |
@@ -1560,22 +1557,33 @@ static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
if (kvm_lapic_lvt_supported(apic, LVT_CMCI))
valid_reg_mask |= APIC_REG_MASK(APIC_LVTCMCI);
- /*
- * ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. WARN if KVM
- * reads ICR in x2APIC mode as it's an 8-byte register in x2APIC and
- * needs to be manually handled by the caller.
- */
+ /* ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. */
if (!apic_x2apic_mode(apic))
valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI) |
APIC_REG_MASK(APIC_DFR) |
APIC_REG_MASK(APIC_ICR2);
- else
- WARN_ON_ONCE(offset == APIC_ICR);
+
+ return valid_reg_mask;
+}
+EXPORT_SYMBOL_GPL(kvm_lapic_readable_reg_mask);
+
+static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
+ void *data)
+{
+ unsigned char alignment = offset & 0xf;
+ u32 result;
+
+ /*
+ * WARN if KVM reads ICR in x2APIC mode, as it's an 8-byte register in
+ * x2APIC and needs to be manually handled by the caller.
+ */
+ WARN_ON_ONCE(apic_x2apic_mode(apic) && offset == APIC_ICR);
if (alignment + len > 4)
return 1;
- if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
+ if (offset > 0x3f0 ||
+ !(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset)))
return 1;
result = __apic_read(apic, offset & ~0xf);
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index df316ede7546..0a0ea4b5dd8c 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -146,6 +146,8 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
void kvm_lapic_exit(void);
+u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
+
#define VEC_POS(v) ((v) & (32 - 1))
#define REG_POS(v) (((v) >> 5) << 4)
--
2.39.0.314.g84b9a713c41-googOn Sat, 2023-01-07 at 01:10 +0000, Sean Christopherson wrote:
> Move the generation of the readable APIC regs bitmask to a standalone
> helper so that VMX can use the mask for its MSR interception bitmaps.
>
> No functional change intended.
>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
> arch/x86/kvm/lapic.c | 34 +++++++++++++++++++++-------------
> arch/x86/kvm/lapic.h | 2 ++
> 2 files changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index c49b13418638..19697fe9b2c7 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -1529,12 +1529,9 @@ static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
> #define APIC_REGS_MASK(first, count) \
> (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
>
> -static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
> - void *data)
> +u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic)
> {
> - unsigned char alignment = offset & 0xf;
> - u32 result;
> - /* this bitmask has a bit cleared for each reserved register */
> + /* Leave bits '0' for reserved and write-only registers. */
> u64 valid_reg_mask =
> APIC_REG_MASK(APIC_ID) |
> APIC_REG_MASK(APIC_LVR) |
> @@ -1560,22 +1557,33 @@ static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
> if (kvm_lapic_lvt_supported(apic, LVT_CMCI))
> valid_reg_mask |= APIC_REG_MASK(APIC_LVTCMCI);
>
> - /*
> - * ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. WARN if KVM
> - * reads ICR in x2APIC mode as it's an 8-byte register in x2APIC and
> - * needs to be manually handled by the caller.
> - */
> + /* ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. */
> if (!apic_x2apic_mode(apic))
> valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI) |
> APIC_REG_MASK(APIC_DFR) |
> APIC_REG_MASK(APIC_ICR2);
> - else
> - WARN_ON_ONCE(offset == APIC_ICR);
> +
> + return valid_reg_mask;
> +}
> +EXPORT_SYMBOL_GPL(kvm_lapic_readable_reg_mask);
> +
> +static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
> + void *data)
> +{
> + unsigned char alignment = offset & 0xf;
> + u32 result;
> +
> + /*
> + * WARN if KVM reads ICR in x2APIC mode, as it's an 8-byte register in
> + * x2APIC and needs to be manually handled by the caller.
> + */
> + WARN_ON_ONCE(apic_x2apic_mode(apic) && offset == APIC_ICR);
>
> if (alignment + len > 4)
> return 1;
>
> - if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
> + if (offset > 0x3f0 ||
> + !(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset)))
> return 1;
>
> result = __apic_read(apic, offset & ~0xf);
> diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
> index df316ede7546..0a0ea4b5dd8c 100644
> --- a/arch/x86/kvm/lapic.h
> +++ b/arch/x86/kvm/lapic.h
> @@ -146,6 +146,8 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
> int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
> void kvm_lapic_exit(void);
>
> +u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
> +
> #define VEC_POS(v) ((v) & (32 - 1))
> #define REG_POS(v) (((v) >> 5) << 4)
>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Best regards,
Maxim Levitsky
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