From nobody Tue Sep 16 04:35:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 845CDC5479D for ; Sat, 7 Jan 2023 01:11:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235746AbjAGBK6 (ORCPT ); Fri, 6 Jan 2023 20:10:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236798AbjAGBKi (ORCPT ); Fri, 6 Jan 2023 20:10:38 -0500 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00542848D5 for ; Fri, 6 Jan 2023 17:10:35 -0800 (PST) Received: by mail-pj1-x1049.google.com with SMTP id z4-20020a17090ab10400b002195a146546so3826217pjq.9 for ; Fri, 06 Jan 2023 17:10:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=ytl00DlerGscM1Z2s2nAhDtn5opR5GZn7robSFrZWZY=; b=MfxUKpWUJ1zSJQHSCeUHIcVc8OawjLuZjKMS1fzXz+zYl32lKol+qKMauguiR5vYqV cHCSulvbxQhF8LgBzOWfgUBdV4zhhP6CWfEUnCQrWOT5RdvEap0UkoClBPPocPiFBoUl L4F+KvkbcGk/adXM0WZTWqXuXJbGB90vh9gNpB9i3fVF5CwsgoFZQWg1jzTI1yVan/rj 8kNYdDdaiBTVKubzEv6eexqqceQRZHZy0Pfj7ibPF8TM8fZeesp4Bs2qtTycaPeG/bSZ hrLWtIOC1n4oZ2TIq0+19Fba5y+230omi0hagx+ythej4bk2tfzK7H5XpVUUXDe7zkUE r+5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ytl00DlerGscM1Z2s2nAhDtn5opR5GZn7robSFrZWZY=; b=Hbi6Ouqm3IbNeRcGhFKUDD0s3o55vrNdICgjprHxqQmqoUxsibCunrsKDJ76M664G2 ZWrbYihai0uLNuT9yIx2PWm/BGRL6DPAgTRsa+voC7eoZPN6AlN1s0uc4W652kZMSdw0 D/+8kCJEKM0V3+bsvfSIhsJ8QkwJfGAPvSMmkPIszU8J0Py5skI2EWCIAxNMOkZXwkFf bIqsxopMP+2n0HKO2xCa4cy+uVy4UUq96gxJjY32P6XnKiKRkiMuhbe8ETL8WAW0J9sz PNmJE5whAnrYqbIkZUQXPELRE/pzhIHoGRGJnsomK6a6WBhHtLBxN7T5ZggRbVOnOhz0 xMvQ== X-Gm-Message-State: AFqh2krdgbB/OHFXe2jxVfZ3By4xXEJET/diQ/96ER0nbKVeR/MoF/Dz NEnxu3aYLXPant+aUpa8Ap9hoZadUZU= X-Google-Smtp-Source: AMrXdXtQ4Ak35Lb34wlJ+kqfXpwqQmaTB1EiKJZqxY0/z0Y2spI3fFkKlj6H7g+5x+h8/JI+XU3gIl+YQd4= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:90a:f985:b0:223:9019:6996 with SMTP id cq5-20020a17090af98500b0022390196996mr4325710pjb.204.1673053835513; Fri, 06 Jan 2023 17:10:35 -0800 (PST) Reply-To: Sean Christopherson Date: Sat, 7 Jan 2023 01:10:23 +0000 In-Reply-To: <20230107011025.565472-1-seanjc@google.com> Mime-Version: 1.0 References: <20230107011025.565472-1-seanjc@google.com> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Message-ID: <20230107011025.565472-5-seanjc@google.com> Subject: [PATCH 4/6] KVM: x86: Split out logic to generate "readable" APIC regs mask to helper From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Orr , Ben Gardon , Venkatesh Srinivas Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the generation of the readable APIC regs bitmask to a standalone helper so that VMX can use the mask for its MSR interception bitmaps. No functional change intended. Signed-off-by: Sean Christopherson Reviewed-by: Maxim Levitsky --- arch/x86/kvm/lapic.c | 34 +++++++++++++++++++++------------- arch/x86/kvm/lapic.h | 2 ++ 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index c49b13418638..19697fe9b2c7 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1529,12 +1529,9 @@ static inline struct kvm_lapic *to_lapic(struct kvm_= io_device *dev) #define APIC_REGS_MASK(first, count) \ (APIC_REG_MASK(first) * ((1ull << (count)) - 1)) =20 -static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, - void *data) +u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic) { - unsigned char alignment =3D offset & 0xf; - u32 result; - /* this bitmask has a bit cleared for each reserved register */ + /* Leave bits '0' for reserved and write-only registers. */ u64 valid_reg_mask =3D APIC_REG_MASK(APIC_ID) | APIC_REG_MASK(APIC_LVR) | @@ -1560,22 +1557,33 @@ static int kvm_lapic_reg_read(struct kvm_lapic *api= c, u32 offset, int len, if (kvm_lapic_lvt_supported(apic, LVT_CMCI)) valid_reg_mask |=3D APIC_REG_MASK(APIC_LVTCMCI); =20 - /* - * ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. WARN if KVM - * reads ICR in x2APIC mode as it's an 8-byte register in x2APIC and - * needs to be manually handled by the caller. - */ + /* ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. */ if (!apic_x2apic_mode(apic)) valid_reg_mask |=3D APIC_REG_MASK(APIC_ARBPRI) | APIC_REG_MASK(APIC_DFR) | APIC_REG_MASK(APIC_ICR2); - else - WARN_ON_ONCE(offset =3D=3D APIC_ICR); + + return valid_reg_mask; +} +EXPORT_SYMBOL_GPL(kvm_lapic_readable_reg_mask); + +static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, + void *data) +{ + unsigned char alignment =3D offset & 0xf; + u32 result; + + /* + * WARN if KVM reads ICR in x2APIC mode, as it's an 8-byte register in + * x2APIC and needs to be manually handled by the caller. + */ + WARN_ON_ONCE(apic_x2apic_mode(apic) && offset =3D=3D APIC_ICR); =20 if (alignment + len > 4) return 1; =20 - if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset))) + if (offset > 0x3f0 || + !(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset))) return 1; =20 result =3D __apic_read(apic, offset & ~0xf); diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index df316ede7546..0a0ea4b5dd8c 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -146,6 +146,8 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 ms= r, u64 *data); int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long le= n); void kvm_lapic_exit(void); =20 +u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic); + #define VEC_POS(v) ((v) & (32 - 1)) #define REG_POS(v) (((v) >> 5) << 4) =20 --=20 2.39.0.314.g84b9a713c41-goog