Add Ethernet controller node for mt8195.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 81 ++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 ++++++++++++++++++++
2 files changed, 167 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
index 4fbd99eb496a..2e6979c47aa6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
@@ -258,6 +258,66 @@ &mt6359_vsram_others_ldo_reg {
};
&pio {
+ eth_default_pins: eth-default-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
+ <PINMUX_GPIO78__FUNC_GBE_TXD2>,
+ <PINMUX_GPIO79__FUNC_GBE_TXD1>,
+ <PINMUX_GPIO80__FUNC_GBE_TXD0>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
+ <PINMUX_GPIO88__FUNC_GBE_TXEN>,
+ <PINMUX_GPIO87__FUNC_GBE_RXDV>,
+ <PINMUX_GPIO86__FUNC_GBE_RXC>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
+ <PINMUX_GPIO82__FUNC_GBE_RXD2>,
+ <PINMUX_GPIO83__FUNC_GBE_RXD1>,
+ <PINMUX_GPIO84__FUNC_GBE_RXD0>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
+ <PINMUX_GPIO90__FUNC_GBE_MDIO>;
+ input-enable;
+ };
+ pins-power {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ output-high;
+ };
+ };
+
+ eth_sleep_pins: eth-sleep-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
+ <PINMUX_GPIO78__FUNC_GPIO78>,
+ <PINMUX_GPIO79__FUNC_GPIO79>,
+ <PINMUX_GPIO80__FUNC_GPIO80>;
+ };
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
+ <PINMUX_GPIO88__FUNC_GPIO88>,
+ <PINMUX_GPIO87__FUNC_GPIO87>,
+ <PINMUX_GPIO86__FUNC_GPIO86>;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
+ <PINMUX_GPIO82__FUNC_GPIO82>,
+ <PINMUX_GPIO83__FUNC_GPIO83>,
+ <PINMUX_GPIO84__FUNC_GPIO84>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
+ <PINMUX_GPIO90__FUNC_GPIO90>;
+ input-disable;
+ bias-disable;
+ };
+ };
+
gpio_keys_pins: gpio-keys-pins {
pins {
pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
@@ -434,6 +494,27 @@ &xhci0 {
status = "okay";
};
+ð {
+ phy-mode ="rgmii-id";
+ phy-handle = <ðernet_phy0>;
+ snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
+ snps,reset-delays-us = <0 10000 10000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <ð_default_pins>;
+ pinctrl-1 = <ð_sleep_pins>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethernet_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ };
+ };
+};
+
&xhci1 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 5d31536f4c48..b90d38d87aa4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1046,6 +1046,92 @@ spis1: spi@1101e000 {
status = "disabled";
};
+ eth: ethernet@11021000 {
+ compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
+ reg = <0 0x11021000 0 0x4000>;
+ interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "macirq";
+ clock-names = "axi",
+ "apb",
+ "mac_main",
+ "ptp_ref",
+ "rmii_internal",
+ "mac_cg";
+ clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
+ <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
+ <&topckgen CLK_TOP_SNPS_ETH_250M>,
+ <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+ <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
+ <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+ assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
+ <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+ <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
+ <&topckgen CLK_TOP_ETHPLL_D8>,
+ <&topckgen CLK_TOP_ETHPLL_D10>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
+ mediatek,pericfg = <&infracfg_ao>;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ snps,clk-csr = <0>;
+ status = "disabled";
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+ snps,tx-sched-wrr;
+ queue0 {
+ snps,weight = <0x10>;
+ snps,dcb-algorithm;
+ snps,priority = <0x0>;
+ };
+ queue1 {
+ snps,weight = <0x11>;
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+ queue2 {
+ snps,weight = <0x12>;
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+ queue3 {
+ snps,weight = <0x13>;
+ snps,dcb-algorithm;
+ snps,priority = <0x3>;
+ };
+ };
+ };
+
xhci0: usb@11200000 {
compatible = "mediatek,mt8195-xhci",
"mediatek,mtk-xhci";
--
2.25.1
> --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > @@ -258,6 +258,66 @@ &mt6359_vsram_others_ldo_reg { > }; > > +ð { > + phy-mode ="rgmii-id"; > + phy-handle = <ðernet_phy0>; > + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; > + snps,reset-delays-us = <0 10000 10000>; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <ð_default_pins>; > + pinctrl-1 = <ð_sleep_pins>; > + status = "okay"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; The mdio bus master is a property of the SoC, not the board. So i would expect it be in the .dtsi file. > + ethernet_phy0: ethernet-phy@1 { > + compatible = "ethernet-phy-id001c.c916"; > + reg = <0x1>; > + }; Is the PHY integrated into the SoC, or on the board? You also don't need the compatible, if the PHY correctly implements the ID registers. Andrew
On Wed, 2022-12-28 at 17:13 +0100, Andrew Lunn wrote: > > --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > > +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts > > @@ -258,6 +258,66 @@ &mt6359_vsram_others_ldo_reg { > > }; > > > > +ð { > > + phy-mode ="rgmii-id"; > > + phy-handle = <ðernet_phy0>; > > + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; > > + snps,reset-delays-us = <0 10000 10000>; > > + pinctrl-names = "default", "sleep"; > > + pinctrl-0 = <ð_default_pins>; > > + pinctrl-1 = <ð_sleep_pins>; > > + status = "okay"; > > + > > + mdio { > > + compatible = "snps,dwmac-mdio"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > The mdio bus master is a property of the SoC, not the board. So i > would expect it be in the .dtsi file. OK, will move mdio to .dtsi. > > > + ethernet_phy0: ethernet-phy@1 { > > + compatible = "ethernet-phy-id001c.c916"; > > + reg = <0x1>; > > + }; > > Is the PHY integrated into the SoC, or on the board? The PHY is on the board, an external device as to SoC. > > You also don't need the compatible, if the PHY correctly implements > the ID registers. But without the compatible, it seems PHY driver will not be attached. How should I do? Thanks in advance. > > Andrew Best Regards! Biao
> > Is the PHY integrated into the SoC, or on the board? > The PHY is on the board, an external device as to SoC. > > > > You also don't need the compatible, if the PHY correctly implements > > the ID registers. > But without the compatible, it seems PHY driver will not be attached. > How should I do? Thanks in advance. Check what happens in mdiobus_scan() and get_phy_device(). When it reads registers 2 and 3, does it get valid ID register contents? Andrew
On Thu, 2022-12-29 at 02:06 +0100, Andrew Lunn wrote: > > > Is the PHY integrated into the SoC, or on the board? > > > > The PHY is on the board, an external device as to SoC. > > > > > > You also don't need the compatible, if the PHY correctly > > > implements > > > the ID registers. > > > > But without the compatible, it seems PHY driver will not be > > attached. > > How should I do? Thanks in advance. > > Check what happens in mdiobus_scan() and get_phy_device(). When it > reads registers 2 and 3, does it get valid ID register contents? Yes, I tried remove the compatible, and PHY driver is attached as expected. I'll remove the phy compatible in next send. > > Andrew As to the "Confidentiality Notice", I have asked our IT to handle it. Hope no such notice now. Best Regards! Biao
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