From nobody Sat Sep 21 09:59:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04835C3DA7A for ; Wed, 28 Dec 2022 06:34:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229695AbiL1Gdx (ORCPT ); Wed, 28 Dec 2022 01:33:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229632AbiL1Gdq (ORCPT ); Wed, 28 Dec 2022 01:33:46 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1459DDF1C; Tue, 27 Dec 2022 22:33:44 -0800 (PST) X-UUID: f71a861c257445f7b3c5f43973b02622-20221228 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jeiiqoqKwFie5MQ4rjQcD5M4/OBETmdj8o2F7jlFF4Q=; b=M4vxxtKvlnEgukVfj7+dNcWRkuPUbggL6Rv+9vnkEhE749tPTGQZVLuwAlULXrIqo6agAtoTIAvYEf1j9hF1Hotzm5iRrP0XUlSp48jt8DRtpZoihoLVWcMAYWF76sKftPEmCZOWMyBJ8lu7v94b37Nlj8cZoRPqZHcYFEK7i2s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:650d08c7-be76-463d-b2fd-112b7f675618,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.14,REQID:650d08c7-be76-463d-b2fd-112b7f675618,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:dcaaed0,CLOUDID:689c0053-dd49-462e-a4be-2143a3ddc739,B ulkID:221228143340FL0QRH0H,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: f71a861c257445f7b3c5f43973b02622-20221228 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 548425063; Wed, 28 Dec 2022 14:33:37 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 28 Dec 2022 14:33:36 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 28 Dec 2022 14:33:35 +0800 From: Biao Huang To: Andrew Lunn , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Richard Cochran , , , , , Biao Huang , Subject: [PATCH v6 2/2] arm64: dts: mt8195: Add Ethernet controller Date: Wed, 28 Dec 2022 14:33:30 +0800 Message-ID: <20221228063331.10756-3-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228063331.10756-1-biao.huang@mediatek.com> References: <20221228063331.10756-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Ethernet controller node for mt8195. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Biao Huang --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 81 ++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 ++++++++++++++++++++ 2 files changed, 167 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot= /dts/mediatek/mt8195-demo.dts index 4fbd99eb496a..2e6979c47aa6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -258,6 +258,66 @@ &mt6359_vsram_others_ldo_reg { }; =20 &pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux =3D , + , + , + ; + drive-strength =3D ; + }; + pins-cc { + pinmux =3D , + , + , + ; + drive-strength =3D ; + }; + pins-rxd { + pinmux =3D , + , + , + ; + }; + pins-mdio { + pinmux =3D , + ; + input-enable; + }; + pins-power { + pinmux =3D , + ; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux =3D , + , + , + ; + }; + pins-cc { + pinmux =3D , + , + , + ; + }; + pins-rxd { + pinmux =3D , + , + , + ; + }; + pins-mdio { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + }; + gpio_keys_pins: gpio-keys-pins { pins { pinmux =3D ; @@ -434,6 +494,27 @@ &xhci0 { status =3D "okay"; }; =20 +ð { + phy-mode =3D"rgmii-id"; + phy-handle =3D <ðernet_phy0>; + snps,reset-gpio =3D <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us =3D <0 10000 10000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ð_default_pins>; + pinctrl-1 =3D <ð_sleep_pins>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + ethernet_phy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-id001c.c916"; + reg =3D <0x1>; + }; + }; +}; + &xhci1 { vusb33-supply =3D <&mt6359_vusb_ldo_reg>; status =3D "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 5d31536f4c48..b90d38d87aa4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1046,6 +1046,92 @@ spis1: spi@1101e000 { status =3D "disabled"; }; =20 + eth: ethernet@11021000 { + compatible =3D "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg =3D <0 0x11021000 0 0x4000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clock-names =3D "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal", + "mac_cg"; + clocks =3D <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + assigned-clocks =3D <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg =3D <&infracfg_ao>; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + snps,clk-csr =3D <0>; + status =3D "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0x7>; + snps,rd_osr_lmt =3D <0x7>; + snps,blen =3D <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x0>; + }; + queue1 { + snps,weight =3D <0x11>; + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + queue2 { + snps,weight =3D <0x12>; + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + queue3 { + snps,weight =3D <0x13>; + snps,dcb-algorithm; + snps,priority =3D <0x3>; + }; + }; + }; + xhci0: usb@11200000 { compatible =3D "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; --=20 2.25.1