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[PATCH v3 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping

Johnson Wang posted 4 patches 3 years, 4 months ago
There is a newer version of this series
[PATCH v3 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping
Posted by Johnson Wang 3 years, 4 months ago 
Add the new binding documentation for MediaTek frequency hopping
and spread spectrum clocking control.

Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
---
 .../arm/mediatek/mediatek,mt8186-fhctl.yaml   | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
new file mode 100644
index 000000000000..258dff7ce6bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-fhctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek frequency hopping and spread spectrum clocking control
+
+maintainers:
+  - Edward-JW Yang <edward-jw.yang@mediatek.com>
+
+description: |
+  Frequency hopping control (FHCTL) is a piece of hardware that control
+  some PLLs to adopt "hopping" mechanism to adjust their frequency.
+  Spread spectrum clocking (SSC) is another function provided by this hardware.
+
+properties:
+  compatible:
+    const: mediatek,mt8186-fhctl
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description: Phandles of the PLL with FHCTL hardware capability.
+    minItems: 1
+    maxItems: 30
+
+  mediatek,hopping-ssc-percent:
+    description: The percentage of spread spectrum clocking for one PLL.
+    minItems: 1
+    maxItems: 30
+    items:
+      default: 0
+      minimum: 0
+      maximum: 8
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8186-clk.h>
+    fhctl: fhctl@1000ce00 {
+        compatible = "mediatek,mt8186-fhctl";
+        reg = <0x1000c000 0xe00>;
+        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
+        mediatek,hopping-ssc-percent = <3>;
+    };
-- 
2.18.0
Re: [PATCH v3 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping
Posted by Rob Herring 3 years, 4 months ago 
On Thu, 29 Sep 2022 19:46:22 +0800, Johnson Wang wrote:
> Add the new binding documentation for MediaTek frequency hopping
> and spread spectrum clocking control.
> 
> Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> ---
>  .../arm/mediatek/mediatek,mt8186-fhctl.yaml   | 53 +++++++++++++++++++
>  1 file changed, 53 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>
Re: [PATCH v3 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping
Posted by AngeloGioacchino Del Regno 3 years, 4 months ago 
Il 29/09/22 13:46, Johnson Wang ha scritto:
> Add the new binding documentation for MediaTek frequency hopping
> and spread spectrum clocking control.
> 
> Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> ---
>   .../arm/mediatek/mediatek,mt8186-fhctl.yaml   | 53 +++++++++++++++++++
>   1 file changed, 53 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
> new file mode 100644
> index 000000000000..258dff7ce6bc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-fhctl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek frequency hopping and spread spectrum clocking control
> +
> +maintainers:
> +  - Edward-JW Yang <edward-jw.yang@mediatek.com>
> +
> +description: |
> +  Frequency hopping control (FHCTL) is a piece of hardware that control
> +  some PLLs to adopt "hopping" mechanism to adjust their frequency.
> +  Spread spectrum clocking (SSC) is another function provided by this hardware.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8186-fhctl
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    description: Phandles of the PLL with FHCTL hardware capability.
> +    minItems: 1
> +    maxItems: 30
> +
> +  mediatek,hopping-ssc-percent:
> +    description: The percentage of spread spectrum clocking for one PLL.
> +    minItems: 1
> +    maxItems: 30
> +    items:
> +      default: 0
> +      minimum: 0
> +      maximum: 8
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8186-clk.h>
> +    fhctl: fhctl@1000ce00 {
> +        compatible = "mediatek,mt8186-fhctl";
> +        reg = <0x1000c000 0xe00>;
> +        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
> +        mediatek,hopping-ssc-percent = <3>;
> +    };


.... a more realistic example:

     #include <dt-bindings/clock/mt8186-clk.h>

     soc {
         #address-cells = <2>;
         #size-cells = <2>;

         fhctl: fhctl@1000ce00 {
             compatible = "mediatek,mt8186-fhctl";
             reg = <0 0x1000c000 0 0xe00>;
             clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
             mediatek,hopping-ssc-percent = <3>;
         };
     };

After which...

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Re: [PATCH v3 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping
Posted by Rob Herring 3 years, 4 months ago 
On Thu, Sep 29, 2022 at 03:07:49PM +0200, AngeloGioacchino Del Regno wrote:
> Il 29/09/22 13:46, Johnson Wang ha scritto:
> > Add the new binding documentation for MediaTek frequency hopping
> > and spread spectrum clocking control.
> > 
> > Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> > Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > ---
> >   .../arm/mediatek/mediatek,mt8186-fhctl.yaml   | 53 +++++++++++++++++++
> >   1 file changed, 53 insertions(+)
> >   create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
> > new file mode 100644
> > index 000000000000..258dff7ce6bc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
> > @@ -0,0 +1,53 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-fhctl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek frequency hopping and spread spectrum clocking control
> > +
> > +maintainers:
> > +  - Edward-JW Yang <edward-jw.yang@mediatek.com>
> > +
> > +description: |
> > +  Frequency hopping control (FHCTL) is a piece of hardware that control
> > +  some PLLs to adopt "hopping" mechanism to adjust their frequency.
> > +  Spread spectrum clocking (SSC) is another function provided by this hardware.
> > +
> > +properties:
> > +  compatible:
> > +    const: mediatek,mt8186-fhctl
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    description: Phandles of the PLL with FHCTL hardware capability.
> > +    minItems: 1
> > +    maxItems: 30
> > +
> > +  mediatek,hopping-ssc-percent:
> > +    description: The percentage of spread spectrum clocking for one PLL.
> > +    minItems: 1
> > +    maxItems: 30
> > +    items:
> > +      default: 0
> > +      minimum: 0
> > +      maximum: 8
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/mt8186-clk.h>
> > +    fhctl: fhctl@1000ce00 {
> > +        compatible = "mediatek,mt8186-fhctl";
> > +        reg = <0x1000c000 0xe00>;
> > +        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
> > +        mediatek,hopping-ssc-percent = <3>;
> > +    };
> 
> 
> .... a more realistic example:

One or 2 cells is really outside the scope of the binding as either is 
valid. If the parent bus only has 32-bits of address space, there's 
little reason to use 2 cells.

> 
>     #include <dt-bindings/clock/mt8186-clk.h>
> 
>     soc {
>         #address-cells = <2>;
>         #size-cells = <2>;
> 
>         fhctl: fhctl@1000ce00 {
>             compatible = "mediatek,mt8186-fhctl";
>             reg = <0 0x1000c000 0 0xe00>;
>             clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
>             mediatek,hopping-ssc-percent = <3>;
>         };
>     };
> 
> After which...
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
Re: [PATCH v3 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping
Posted by Johnson Wang (王聖鑫) 3 years, 4 months ago 
On Fri, 2022-09-30 at 14:07 -0500, Rob Herring wrote:
> On Thu, Sep 29, 2022 at 03:07:49PM +0200, AngeloGioacchino Del Regno
> wrote:
> > Il 29/09/22 13:46, Johnson Wang ha scritto:
> > > Add the new binding documentation for MediaTek frequency hopping
> > > and spread spectrum clocking control.
> > > 
> > > Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> > > Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> > > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > > ---
> > >   .../arm/mediatek/mediatek,mt8186-fhctl.yaml   | 53
> > > +++++++++++++++++++
> > >   1 file changed, 53 insertions(+)
> > >   create mode 100644
> > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > fhctl.yaml
> > > 
> > > diff --git
> > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > fhctl.yaml
> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > fhctl.yaml
> > > new file mode 100644
> > > index 000000000000..258dff7ce6bc
> > > --- /dev/null
> > > +++
> > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
> > > fhctl.yaml
> > > @@ -0,0 +1,53 @@
> > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: 
> > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-fhctl.yaml*__;Iw!!CTRNKA9wMg0ARbw!xVt73f8PaQKph8n0ffGHHmQIxdzooUtGr0xDNVqy_6V0vwcs5k-FLrmkB3PZupSu1ciC$
> > >  
> > > +$schema: 
> > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!xVt73f8PaQKph8n0ffGHHmQIxdzooUtGr0xDNVqy_6V0vwcs5k-FLrmkB3PZulXwBACk$
> > >  
> > > +
> > > +title: MediaTek frequency hopping and spread spectrum clocking
> > > control
> > > +
> > > +maintainers:
> > > +  - Edward-JW Yang <edward-jw.yang@mediatek.com>
> > > +
> > > +description: |
> > > +  Frequency hopping control (FHCTL) is a piece of hardware that
> > > control
> > > +  some PLLs to adopt "hopping" mechanism to adjust their
> > > frequency.
> > > +  Spread spectrum clocking (SSC) is another function provided by
> > > this hardware.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: mediatek,mt8186-fhctl
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +  clocks:
> > > +    description: Phandles of the PLL with FHCTL hardware
> > > capability.
> > > +    minItems: 1
> > > +    maxItems: 30
> > > +
> > > +  mediatek,hopping-ssc-percent:
> > > +    description: The percentage of spread spectrum clocking for
> > > one PLL.
> > > +    minItems: 1
> > > +    maxItems: 30
> > > +    items:
> > > +      default: 0
> > > +      minimum: 0
> > > +      maximum: 8
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > > +  - clocks
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/clock/mt8186-clk.h>
> > > +    fhctl: fhctl@1000ce00 {
> > > +        compatible = "mediatek,mt8186-fhctl";
> > > +        reg = <0x1000c000 0xe00>;
> > > +        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
> > > +        mediatek,hopping-ssc-percent = <3>;
> > > +    };
> > 
> > 
> > .... a more realistic example:
> 
> One or 2 cells is really outside the scope of the binding as either
> is 
> valid. If the parent bus only has 32-bits of address space, there's 
> little reason to use 2 cells.
> 

Hi Rob,

Thanks for the explanation.

Then I will keep this example the same in the next version.

BRs,
Johnson Wang
> > 
> >     #include <dt-bindings/clock/mt8186-clk.h>
> > 
> >     soc {
> >         #address-cells = <2>;
> >         #size-cells = <2>;
> > 
> >         fhctl: fhctl@1000ce00 {
> >             compatible = "mediatek,mt8186-fhctl";
> >             reg = <0 0x1000c000 0 0xe00>;
> >             clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
> >             mediatek,hopping-ssc-percent = <3>;
> >         };
> >     };
> > 
> > After which...
> > 
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> >
Re: [PATCH v3 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping
Posted by AngeloGioacchino Del Regno 3 years, 4 months ago 
Il 06/10/22 13:23, Johnson Wang (王聖鑫) ha scritto:
> On Fri, 2022-09-30 at 14:07 -0500, Rob Herring wrote:
>> On Thu, Sep 29, 2022 at 03:07:49PM +0200, AngeloGioacchino Del Regno
>> wrote:
>>> Il 29/09/22 13:46, Johnson Wang ha scritto:
>>>> Add the new binding documentation for MediaTek frequency hopping
>>>> and spread spectrum clocking control.
>>>>
>>>> Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
>>>> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
>>>> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
>>>> ---
>>>>    .../arm/mediatek/mediatek,mt8186-fhctl.yaml   | 53
>>>> +++++++++++++++++++
>>>>    1 file changed, 53 insertions(+)
>>>>    create mode 100644
>>>> Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
>>>> fhctl.yaml
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
>>>> fhctl.yaml
>>>> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
>>>> fhctl.yaml
>>>> new file mode 100644
>>>> index 000000000000..258dff7ce6bc
>>>> --- /dev/null
>>>> +++
>>>> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-
>>>> fhctl.yaml
>>>> @@ -0,0 +1,53 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id:
>>>> https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-fhctl.yaml*__;Iw!!CTRNKA9wMg0ARbw!xVt73f8PaQKph8n0ffGHHmQIxdzooUtGr0xDNVqy_6V0vwcs5k-FLrmkB3PZupSu1ciC$
>>>>   
>>>> +$schema:
>>>> https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!xVt73f8PaQKph8n0ffGHHmQIxdzooUtGr0xDNVqy_6V0vwcs5k-FLrmkB3PZulXwBACk$
>>>>   
>>>> +
>>>> +title: MediaTek frequency hopping and spread spectrum clocking
>>>> control
>>>> +
>>>> +maintainers:
>>>> +  - Edward-JW Yang <edward-jw.yang@mediatek.com>
>>>> +
>>>> +description: |
>>>> +  Frequency hopping control (FHCTL) is a piece of hardware that
>>>> control
>>>> +  some PLLs to adopt "hopping" mechanism to adjust their
>>>> frequency.
>>>> +  Spread spectrum clocking (SSC) is another function provided by
>>>> this hardware.
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    const: mediatek,mt8186-fhctl
>>>> +
>>>> +  reg:
>>>> +    maxItems: 1
>>>> +
>>>> +  clocks:
>>>> +    description: Phandles of the PLL with FHCTL hardware
>>>> capability.
>>>> +    minItems: 1
>>>> +    maxItems: 30
>>>> +
>>>> +  mediatek,hopping-ssc-percent:
>>>> +    description: The percentage of spread spectrum clocking for
>>>> one PLL.
>>>> +    minItems: 1
>>>> +    maxItems: 30
>>>> +    items:
>>>> +      default: 0
>>>> +      minimum: 0
>>>> +      maximum: 8
>>>> +
>>>> +required:
>>>> +  - compatible
>>>> +  - reg
>>>> +  - clocks
>>>> +
>>>> +additionalProperties: false
>>>> +
>>>> +examples:
>>>> +  - |
>>>> +    #include <dt-bindings/clock/mt8186-clk.h>
>>>> +    fhctl: fhctl@1000ce00 {
>>>> +        compatible = "mediatek,mt8186-fhctl";
>>>> +        reg = <0x1000c000 0xe00>;
>>>> +        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
>>>> +        mediatek,hopping-ssc-percent = <3>;
>>>> +    };
>>>
>>>
>>> .... a more realistic example:
>>
>> One or 2 cells is really outside the scope of the binding as either
>> is
>> valid. If the parent bus only has 32-bits of address space, there's
>> little reason to use 2 cells.
>>
> 
> Hi Rob,
> 
> Thanks for the explanation.
> 
> Then I will keep this example the same in the next version.

That was just to have it 1:1 with how it'll be written in the devicetree....
....in any case, Johnson, there's a discrepancy in the iospace:
1000ce00 vs 0c1000c000 - that has to be fixed anyway.

Cheers,
Angelo

> 
> BRs,
> Johnson Wang
>>>
>>>      #include <dt-bindings/clock/mt8186-clk.h>
>>>
>>>      soc {
>>>          #address-cells = <2>;
>>>          #size-cells = <2>;
>>>
>>>          fhctl: fhctl@1000ce00 {
>>>              compatible = "mediatek,mt8186-fhctl";
>>>              reg = <0 0x1000c000 0 0xe00>;
>>>              clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
>>>              mediatek,hopping-ssc-percent = <3>;
>>>          };
>>>      };
>>>
>>> After which...
>>>
>>> Reviewed-by: AngeloGioacchino Del Regno <
>>> angelogioacchino.delregno@collabora.com>
>>>
Re: [PATCH v3 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping
Posted by Johnson Wang (王聖鑫) 3 years, 3 months ago 
On Thu, 2022-10-06 at 14:33 +0200, AngeloGioacchino Del Regno wrote:
> Il 06/10/22 13:23, Johnson Wang (王聖鑫) ha scritto:
> > On Fri, 2022-09-30 at 14:07 -0500, Rob Herring wrote:
> > > On Thu, Sep 29, 2022 at 03:07:49PM +0200, AngeloGioacchino Del
> > > Regno
> > > wrote:
> > > > Il 29/09/22 13:46, Johnson Wang ha scritto:
> > > > > Add the new binding documentation for MediaTek frequency
> > > > > hopping
> > > > > and spread spectrum clocking control.
> > > > > 
> > > > > Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> > > > > Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> > > > > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > > > > ---
> > > > >    .../arm/mediatek/mediatek,mt8186-fhctl.yaml   | 53
> > > > > +++++++++++++++++++
> > > > >    1 file changed, 53 insertions(+)
> > > > >    create mode 100644
> > > > > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt818
> > > > > 6-
> > > > > fhctl.yaml
> > > > > 
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8
> > > > > 186-
> > > > > fhctl.yaml
> > > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8
> > > > > 186-
> > > > > fhctl.yaml
> > > > > new file mode 100644
> > > > > index 000000000000..258dff7ce6bc
> > > > > --- /dev/null
> > > > > +++
> > > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8
> > > > > 186-
> > > > > fhctl.yaml
> > > > > @@ -0,0 +1,53 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > > > +%YAML 1.2
> > > > > +---
> > > > > +$id:
> > > > > 
https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-fhctl.yaml*__;Iw!!CTRNKA9wMg0ARbw!xVt73f8PaQKph8n0ffGHHmQIxdzooUtGr0xDNVqy_6V0vwcs5k-FLrmkB3PZupSu1ciC$
> > > > >   
> > > > > +$schema:
> > > > > 
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!xVt73f8PaQKph8n0ffGHHmQIxdzooUtGr0xDNVqy_6V0vwcs5k-FLrmkB3PZulXwBACk$
> > > > >   
> > > > > +
> > > > > +title: MediaTek frequency hopping and spread spectrum
> > > > > clocking
> > > > > control
> > > > > +
> > > > > +maintainers:
> > > > > +  - Edward-JW Yang <edward-jw.yang@mediatek.com>
> > > > > +
> > > > > +description: |
> > > > > +  Frequency hopping control (FHCTL) is a piece of hardware
> > > > > that
> > > > > control
> > > > > +  some PLLs to adopt "hopping" mechanism to adjust their
> > > > > frequency.
> > > > > +  Spread spectrum clocking (SSC) is another function
> > > > > provided by
> > > > > this hardware.
> > > > > +
> > > > > +properties:
> > > > > +  compatible:
> > > > > +    const: mediatek,mt8186-fhctl
> > > > > +
> > > > > +  reg:
> > > > > +    maxItems: 1
> > > > > +
> > > > > +  clocks:
> > > > > +    description: Phandles of the PLL with FHCTL hardware
> > > > > capability.
> > > > > +    minItems: 1
> > > > > +    maxItems: 30
> > > > > +
> > > > > +  mediatek,hopping-ssc-percent:
> > > > > +    description: The percentage of spread spectrum clocking
> > > > > for
> > > > > one PLL.
> > > > > +    minItems: 1
> > > > > +    maxItems: 30
> > > > > +    items:
> > > > > +      default: 0
> > > > > +      minimum: 0
> > > > > +      maximum: 8
> > > > > +
> > > > > +required:
> > > > > +  - compatible
> > > > > +  - reg
> > > > > +  - clocks
> > > > > +
> > > > > +additionalProperties: false
> > > > > +
> > > > > +examples:
> > > > > +  - |
> > > > > +    #include <dt-bindings/clock/mt8186-clk.h>
> > > > > +    fhctl: fhctl@1000ce00 {
> > > > > +        compatible = "mediatek,mt8186-fhctl";
> > > > > +        reg = <0x1000c000 0xe00>;
> > > > > +        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
> > > > > +        mediatek,hopping-ssc-percent = <3>;
> > > > > +    };
> > > > 
> > > > 
> > > > .... a more realistic example:
> > > 
> > > One or 2 cells is really outside the scope of the binding as
> > > either
> > > is
> > > valid. If the parent bus only has 32-bits of address space,
> > > there's
> > > little reason to use 2 cells.
> > > 
> > 
> > Hi Rob,
> > 
> > Thanks for the explanation.
> > 
> > Then I will keep this example the same in the next version.
> 
> That was just to have it 1:1 with how it'll be written in the
> devicetree....
> ....in any case, Johnson, there's a discrepancy in the iospace:
> 1000ce00 vs 0c1000c000 - that has to be fixed anyway.
> 
> Cheers,
> Angelo

Hi Angelo,

Thank you for reminding me.
I didn't notice the iospace typo in the example.

I will fix it in the next version.

BRs,
Johnson Wang
> 
> > 
> > BRs,
> > Johnson Wang
> > > > 
> > > >      #include <dt-bindings/clock/mt8186-clk.h>
> > > > 
> > > >      soc {
> > > >          #address-cells = <2>;
> > > >          #size-cells = <2>;
> > > > 
> > > >          fhctl: fhctl@1000ce00 {
> > > >              compatible = "mediatek,mt8186-fhctl";
> > > >              reg = <0 0x1000c000 0 0xe00>;
> > > >              clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
> > > >              mediatek,hopping-ssc-percent = <3>;
> > > >          };
> > > >      };
> > > > 
> > > > After which...
> > > > 
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > 
> 
>

Patchew 2.1-devel-b67e4c2

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