[PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates

Conor Dooley posted 11 patches 3 years, 2 months ago
.../devicetree/bindings/riscv/microchip.yaml  |  20 +-
arch/riscv/boot/dts/microchip/Makefile        |   2 +
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi |  43 ++++-
.../boot/dts/microchip/mpfs-icicle-kit.dts    |  18 +-
.../dts/microchip/mpfs-m100pfs-fabric.dtsi    |  45 +++++
.../boot/dts/microchip/mpfs-m100pfsevp.dts    | 179 ++++++++++++++++++
.../dts/microchip/mpfs-polarberry-fabric.dtsi |  29 +++
.../dts/microchip/mpfs-sev-kit-fabric.dtsi    |  45 +++++
.../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++
arch/riscv/boot/dts/microchip/mpfs.dtsi       |  30 ---
10 files changed, 511 insertions(+), 45 deletions(-)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
[PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates
Posted by Conor Dooley 3 years, 2 months ago
Resending with an extra patch making some more memory map changes that
are to be introduced in the v2022.10 reference design. Since the
v2022.10 and v2022.09 reference designs both indepedently break
backwards compat, v2022.09 is not compatible with <= v2022.05 and
v2022.10 is not compatible with v2022.09, I am doing the jump directly
to v2022.10 rather than putting an intermediate step at v2022.09.

I did not drop Krzysztof's Ack on patch 1 as s/09/10 has no impact on
the correctness of the binding.

--8<---
Hey all,

Some 6.1 targeted changes here.
Firstly, two new dev kits (one first-party & one from Aries Embedded).
They've been sitting in our vendor tree, so are being sent where they
belong.

Secondly, another release of our reference design for the Icicle kit
is due in September. Usually these do not really change much for the
devicetree, but this time around a pair of changes impact the memory
map.

The first of these is adding dma-ranges to the pcie controller. The
controller had some issues to begin with & with the current reference
design (v2022.05) would not work with mainline Linux nor has it since
reference design v2021.08. A combination of the property, a change
to the FPGA design & a small fix to the driver will get it working
with mainline again. The other non-backwards compatible change to the
reference design is moves of the peripherals instantiated in the
fabric. Currently they are fairly spread out & a common complaint has
been that this leaves little room in the fic3 section of the memory map
for custom peripherals without removing the existing ones.

This series depends on [0] so as not to add dtbs_check warnings. The
fabric clock support is added by [1].

Thanks,
Conor.

Changes since v5:
- swap v2022.09 for v2022.10 in the binding
- add a patch with the v2022.10 memory map changes

Changes since v4:
- fix the incompatible interrupts on m100pfsevp

Changes since v3:
- add an extra patch reducing the fic3 clock rate

Changes since v2:
- drop the sd & emmc versions of the aries devicetree
- remove a extra newline

Changes since v1:
- made the polarberry part of an enum in patch 1

0 - https://lore.kernel.org/linux-gpio/20220825143522.3102546-1-conor.dooley@microchip.com/
1 - https://lore.kernel.org/linux-clk/20220824093342.187844-1-conor.dooley@microchip.com/

Conor Dooley (9):
  dt-bindings: riscv: microchip: document icicle reference design
  dt-bindings: riscv: microchip: document the aries m100pfsevp
  riscv: dts: microchip: add pci dma ranges for the icicle kit
  riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
  riscv: dts: microchip: icicle: update pci address properties
  riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
  riscv: dts: microchip: reduce the fic3 clock rate
  riscv: dts: microchip: add a devicetree for aries' m100pfsevp
  riscv: dts: microchip: update memory configuration for v2022.10

Shravan Chippa (1):
  dt-bindings: riscv: microchip: document the sev kit

Vattipalli Praveen (1):
  riscv: dts: microchip: add sevkit device tree

 .../devicetree/bindings/riscv/microchip.yaml  |  20 +-
 arch/riscv/boot/dts/microchip/Makefile        |   2 +
 .../dts/microchip/mpfs-icicle-kit-fabric.dtsi |  43 ++++-
 .../boot/dts/microchip/mpfs-icicle-kit.dts    |  18 +-
 .../dts/microchip/mpfs-m100pfs-fabric.dtsi    |  45 +++++
 .../boot/dts/microchip/mpfs-m100pfsevp.dts    | 179 ++++++++++++++++++
 .../dts/microchip/mpfs-polarberry-fabric.dtsi |  29 +++
 .../dts/microchip/mpfs-sev-kit-fabric.dtsi    |  45 +++++
 .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++
 arch/riscv/boot/dts/microchip/mpfs.dtsi       |  30 ---
 10 files changed, 511 insertions(+), 45 deletions(-)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts

-- 
2.37.3
Re: [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates
Posted by Conor Dooley 3 years, 2 months ago
On Tue, Sep 27, 2022 at 12:19:12PM +0100, Conor Dooley wrote:
> Resending with an extra patch making some more memory map changes that
> are to be introduced in the v2022.10 reference design. Since the
> v2022.10 and v2022.09 reference designs both indepedently break
> backwards compat, v2022.09 is not compatible with <= v2022.05 and
> v2022.10 is not compatible with v2022.09, I am doing the jump directly
> to v2022.10 rather than putting an intermediate step at v2022.09.
> 
> I did not drop Krzysztof's Ack on patch 1 as s/09/10 has no impact on
> the correctness of the binding.

I had already applied v5, but I am going to apply this version instead.
I will send a PR once the v2022.10 reference design has been released on
the PolarFire SoC GitHub.

Thanks,
Conor.

> 
> --8<---
> Hey all,
> 
> Some 6.1 targeted changes here.
> Firstly, two new dev kits (one first-party & one from Aries Embedded).
> They've been sitting in our vendor tree, so are being sent where they
> belong.
> 
> Secondly, another release of our reference design for the Icicle kit
> is due in September. Usually these do not really change much for the
> devicetree, but this time around a pair of changes impact the memory
> map.
> 
> The first of these is adding dma-ranges to the pcie controller. The
> controller had some issues to begin with & with the current reference
> design (v2022.05) would not work with mainline Linux nor has it since
> reference design v2021.08. A combination of the property, a change
> to the FPGA design & a small fix to the driver will get it working
> with mainline again. The other non-backwards compatible change to the
> reference design is moves of the peripherals instantiated in the
> fabric. Currently they are fairly spread out & a common complaint has
> been that this leaves little room in the fic3 section of the memory map
> for custom peripherals without removing the existing ones.
> 
> This series depends on [0] so as not to add dtbs_check warnings. The
> fabric clock support is added by [1].
> 
> Thanks,
> Conor.
> 
> Changes since v5:
> - swap v2022.09 for v2022.10 in the binding
> - add a patch with the v2022.10 memory map changes
> 
> Changes since v4:
> - fix the incompatible interrupts on m100pfsevp
> 
> Changes since v3:
> - add an extra patch reducing the fic3 clock rate
> 
> Changes since v2:
> - drop the sd & emmc versions of the aries devicetree
> - remove a extra newline
> 
> Changes since v1:
> - made the polarberry part of an enum in patch 1
> 
> 0 - https://lore.kernel.org/linux-gpio/20220825143522.3102546-1-conor.dooley@microchip.com/
> 1 - https://lore.kernel.org/linux-clk/20220824093342.187844-1-conor.dooley@microchip.com/
> 
> Conor Dooley (9):
>   dt-bindings: riscv: microchip: document icicle reference design
>   dt-bindings: riscv: microchip: document the aries m100pfsevp
>   riscv: dts: microchip: add pci dma ranges for the icicle kit
>   riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
>   riscv: dts: microchip: icicle: update pci address properties
>   riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
>   riscv: dts: microchip: reduce the fic3 clock rate
>   riscv: dts: microchip: add a devicetree for aries' m100pfsevp
>   riscv: dts: microchip: update memory configuration for v2022.10
> 
> Shravan Chippa (1):
>   dt-bindings: riscv: microchip: document the sev kit
> 
> Vattipalli Praveen (1):
>   riscv: dts: microchip: add sevkit device tree
> 
>  .../devicetree/bindings/riscv/microchip.yaml  |  20 +-
>  arch/riscv/boot/dts/microchip/Makefile        |   2 +
>  .../dts/microchip/mpfs-icicle-kit-fabric.dtsi |  43 ++++-
>  .../boot/dts/microchip/mpfs-icicle-kit.dts    |  18 +-
>  .../dts/microchip/mpfs-m100pfs-fabric.dtsi    |  45 +++++
>  .../boot/dts/microchip/mpfs-m100pfsevp.dts    | 179 ++++++++++++++++++
>  .../dts/microchip/mpfs-polarberry-fabric.dtsi |  29 +++
>  .../dts/microchip/mpfs-sev-kit-fabric.dtsi    |  45 +++++
>  .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++
>  arch/riscv/boot/dts/microchip/mpfs.dtsi       |  30 ---
>  10 files changed, 511 insertions(+), 45 deletions(-)
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
> 
> -- 
> 2.37.3
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates
Posted by Conor Dooley 3 years, 2 months ago
From: Conor Dooley <conor.dooley@microchip.com>

On Tue, 27 Sep 2022 12:19:12 +0100, Conor Dooley wrote:
> Resending with an extra patch making some more memory map changes that
> are to be introduced in the v2022.10 reference design. Since the
> v2022.10 and v2022.09 reference designs both indepedently break
> backwards compat, v2022.09 is not compatible with <= v2022.05 and
> v2022.10 is not compatible with v2022.09, I am doing the jump directly
> to v2022.10 rather than putting an intermediate step at v2022.09.
> 
> [...]

Applied to dt-for-next (in place of v5). As I pointed out earlier, I
will not make a PR for this until the reference design is available
on the PolarFire SoC GitHub.

[01/11] dt-bindings: riscv: microchip: document icicle reference design
        https://git.kernel.org/conor/c/a0d49a8f77f2
[02/11] dt-bindings: riscv: microchip: document the aries m100pfsevp
        https://git.kernel.org/conor/c/0ebdc51787db
[03/11] dt-bindings: riscv: microchip: document the sev kit
        https://git.kernel.org/conor/c/db3d481698ef
[04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit
        https://git.kernel.org/conor/c/f890e67f292d
[05/11] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
        https://git.kernel.org/conor/c/99d451a7db16
[06/11] riscv: dts: microchip: icicle: update pci address properties
        https://git.kernel.org/conor/c/6fc655ed4986
[07/11] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
        https://git.kernel.org/conor/c/ab291621a8b8
[08/11] riscv: dts: microchip: reduce the fic3 clock rate
        https://git.kernel.org/conor/c/fa52935abef4
[09/11] riscv: dts: microchip: add sevkit device tree
        https://git.kernel.org/conor/c/978a17d1a688
[10/11] riscv: dts: microchip: add a devicetree for aries' m100pfsevp
        https://git.kernel.org/conor/c/d49166646e44
[11/11] riscv: dts: microchip: update memory configuration for v2022.10
        https://git.kernel.org/conor/c/6c1193301791

Thanks,
Conor.