From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D11A4C6FA94 for ; Tue, 27 Sep 2022 11:20:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232070AbiI0LUw (ORCPT ); Tue, 27 Sep 2022 07:20:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230364AbiI0LUO (ORCPT ); Tue, 27 Sep 2022 07:20:14 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 907346F550; Tue, 27 Sep 2022 04:20:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277602; x=1695813602; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6ALKWpCaagUTxOHH47NBdfK1d2p+/P9sFklIuGHcqd0=; b=vWSzZvpCvODQ+eD4DBbMt8iOMKsubWb/EkjEe58J90zkr/V5YYVLbxKM Bz6Kj6ecT10f7UBeUsEf4NsXK0QEgDpU8jKK7NKtZ7YFHcPEGJbHtoYag VaBOiCoS99ssi36Y+MQrFSe0GAiRGSlec7QUNVKwBQrJi0l4aXgGhPuvd xXTUdv0GhT17tttFyW1n7QakneMjSkIPIwdCO9ntIEzEOC1OO/xN+cVNn QKgSYiuBXJrKGYDla7cSRRc/pkbttZl1D84G8VLuQ0ozp5X8QFGWGjIMX 0Fzx0H8B1rw2ziXk3TgBA0q+18yHh4PswgnZlgfsjTWgsHGHplwnB8E3A w==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="182125421" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:19:59 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:19:57 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , , Krzysztof Kozlowski Subject: [PATCH v6 01/11] dt-bindings: riscv: microchip: document icicle reference design Date: Tue, 27 Sep 2022 12:19:13 +0100 Message-ID: <20220927111922.3602838-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The icicle kit reference design's v2022.09 release made some changes to the memory map - including adding the ability to read the fabric clock controllers via the system controller bus & making the PCI controller work with upstream Linux. While the PCI was not working in the v2022.03 design, so nothing is broken there in terms of backwards compatibility, the fabric clocks used in the v2022.03 design were chosen by the individual run of the synthesis tool. In the v2022.09 reference design, the clocks are fixed to use the "north west" fabric Clock Conditioning Circuitry. In the v2022.10 release, the memory map on the DDR side is also changing, so to avoid making a breaking change here twice, jump over the v2022.09 release and straight to the v2022.10 one. Make use of a new compatible to denote that v2022.{09,10} reference design releases are not backwards compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/microchip.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 1aa7336a9672..5c1ad2108049 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -17,12 +17,18 @@ properties: $nodename: const: '/' compatible: - items: - - enum: - - microchip,mpfs-icicle-kit - - microchip,mpfs-icicle-reference-rtlv2203 - - sundance,polarberry - - const: microchip,mpfs + oneOf: + - items: + - enum: + - microchip,mpfs-icicle-reference-rtlv2203 + - microchip,mpfs-icicle-reference-rtlv2210 + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs + + - items: + - enum: + - sundance,polarberry + - const: microchip,mpfs =20 additionalProperties: true =20 --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2FF4C6FA8E for ; Tue, 27 Sep 2022 11:20:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230240AbiI0LUz (ORCPT ); Tue, 27 Sep 2022 07:20:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231958AbiI0LUO (ORCPT ); Tue, 27 Sep 2022 07:20:14 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2542A74BB8; Tue, 27 Sep 2022 04:20:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277604; x=1695813604; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fQJ1JnPi+K+cO2rIgBAMjqRRagg+fMzWNyG9+bWipSQ=; b=r3rttCBtwcWdhblLZMMDqvC5eY6Vbkxvze+Kr1b424GNHiX2vlO6gIcJ e4mVNLV59mMNXdqBi7oVe+RRsG6o4OGFzETE9Iex7iRhWz29HxP/nkzMt 0musftEjuWjFam85cNbHJPO64xP1Attru4mGgBjrR1BeRXAPn3Q6sPSpo +OgR9WTCbR9eqevbuQ1+jpRwl3WcZbviRY5zyukwOZYLcnOA4a/Y/31KY 09nxpVniZx2Qm/18/GpS8ktcfMhfWlCnTKBLTTvR/FCK471b4lknT07iu NI4J8sc/79CRxFUibcld5PtSrOLQgub2S5YR/lrYVh1g+L4h4QTsLaX7n w==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="115596039" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:02 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:00 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , , Rob Herring Subject: [PATCH v6 02/11] dt-bindings: riscv: microchip: document the aries m100pfsevp Date: Tue, 27 Sep 2022 12:19:14 +0100 Message-ID: <20220927111922.3602838-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform. Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-s= om-mpfs025t-pcie-serdes Signed-off-by: Conor Dooley Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 5c1ad2108049..681cedc5578f 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -27,6 +27,7 @@ properties: =20 - items: - enum: + - aries,m100pfsevp - sundance,polarberry - const: microchip,mpfs =20 --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42051C6FA82 for ; Tue, 27 Sep 2022 11:21:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231265AbiI0LVA (ORCPT ); Tue, 27 Sep 2022 07:21:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231976AbiI0LUP (ORCPT ); Tue, 27 Sep 2022 07:20:15 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8E097D1DC; Tue, 27 Sep 2022 04:20:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277608; x=1695813608; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R4jA5Q4br+Ih2J2AV+Bb7Kadubj4iiu5yMNBJvEDQhU=; b=cay70ejNbJxvfQN08K6O2Rs10e4gx/p9agAL6T8b6HHWgK3FoYPpX4qJ /9+cfbZm1hMx/U1zYl6kFzEHujB7CnUjte2ev0abx9uPu4WppcCA2bC/X MbEaLLgXuJTIyUGxC0VSMf73gEDakljVrrs30/euvH7F0MJmmQnCzBl0T +IkXSelb0pB6hUCZqz6z688Ep/jxiqMNpOgoNzr04fQ0y6+ML7CweMW+O JWz3xtGD7NSP4mTC4ajHbK3AGTUIJmLDVkQWkFKOAGOUFVQxXq02Dmed5 U3AWxL0o11Od2oMR0Y3HOOaI+jxphlTkVZPqGlIw214JHHF0trLkEQ+Sy A==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="175776212" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:07 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:05 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:03 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , , Krzysztof Kozlowski Subject: [PATCH v6 03/11] dt-bindings: riscv: microchip: document the sev kit Date: Tue, 27 Sep 2022 12:19:15 +0100 Message-ID: <20220927111922.3602838-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shravan Chippa Update devicetree bindings document with PolarFire SoC Video Kit, known by its "sev-kit" product code. Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77= E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Shravan Chippa Reviewed-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 681cedc5578f..2b8c6a695e99 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - aries,m100pfsevp + - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs =20 --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F988C6FA92 for ; Tue, 27 Sep 2022 11:21:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231817AbiI0LVS (ORCPT ); Tue, 27 Sep 2022 07:21:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230494AbiI0LUX (ORCPT ); Tue, 27 Sep 2022 07:20:23 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C0BFB6023; Tue, 27 Sep 2022 04:20:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277622; x=1695813622; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jGJip5ceUu4A8yJeV6ZmwmmFZ9D61ZjQ1AOYwFa+oXk=; b=07VgAKWacXhY62Xr2soybFfxMekSJQCcbLNb5TQmKKw+wYC5liRqROQ8 3c1ZaHLultvFYHlyTAeKPvCMXVrbzy3Jmj38oUEOCPhemZbSwW3qnHgM5 WWSK6z9UvTTFzVT5R6oKvz0cMschHDAh+GbNHsDKpeTslsOj5UFTp9MI/ ip+2rAZqbjn+wS9MXqyi/C1ZAR+ns/YnArcIF40FF7eOX0tvfSvOjrkNw IHpnm4+U/jIGKihqPjeVA2b0dvBlgCguXRn2ldzeDmMxxcd0iEm7jXGaO QRAFS2w94rVx9xfljLDN3NMJH70Wpr8i4/Ek49v2bR3ifjWogPiqhn7g8 g==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="179094355" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:21 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:08 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:06 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit Date: Tue, 27 Sep 2022 12:19:16 +0100 Message-ID: <20220927111922.3602838-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The recently removed, accidentally included, "matr0" property was used in place of a dma-ranges property. The PCI controller is non-functional with mainline Linux in the v2022.02 or later reference designs and has not worked without configuration of address-translation since v2021.08. Add the address translation that will be used by the v2022.09 reference design & update the compatible used by the dts. Since this change is not backwards compatible, update the compatible to denote this, jumping over v2022.09 directly to v2022.10. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 7 ++++++- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..eec5aba43436 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,7 +2,8 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { - compatible =3D "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpf= s"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 core_pwm0: pwm@41000000 { compatible =3D "microchip,corepwm-rtl-v4"; @@ -37,3 +38,7 @@ fabric_clk1: fabric-clk1 { clock-frequency =3D <125000000>; }; }; + +&pcie { + dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index 044982a11df5..42d350fe6c6b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -11,7 +11,8 @@ =20 / { model =3D "Microchip PolarFire-SoC Icicle Kit"; - compatible =3D "microchip,mpfs-icicle-kit", "microchip,mpfs"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 aliases { ethernet0 =3D &mac1; --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36F97C6FA8E for ; Tue, 27 Sep 2022 11:21:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230369AbiI0LVP (ORCPT ); Tue, 27 Sep 2022 07:21:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231197AbiI0LUZ (ORCPT ); Tue, 27 Sep 2022 07:20:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B5621A83B; Tue, 27 Sep 2022 04:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277623; x=1695813623; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J3Qpg47GGZySRSkluQCg7tca5Lj+SZrqXdSd94Oyz+o=; b=wCHBpCbr/jr7BAtBRy3VMsDPfUBZ9kRYpadcpiTD0QEbWKLAmrbwrL2l nIEcjJROafo1WR4ut9kjWLHMfC0ul2CoFEIuHzQG04Eio5BjgPP+QX0Td bnkip4DhP2wgAW8rw3O9jlnOsJ/7NmWir929ogiU+ILe+VIY/KBuayV7W Uktn/yN04PhUsVLOdSOKqt4OxbbQ3P8wLbpFhZGOikiWLE2XabEbVwgQv xV4IuUfAHujxXeF4lB+p+lvdeNPIhBkWlAtCz8ikZKfUfpwuubLjTETvZ tcUUJDXITbpS4b246qWNU9iHaZQp1BuWngVMuixFy21IWWObq41hAIKzB A==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="179094364" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:22 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:11 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:09 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 05/11] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Date: Tue, 27 Sep 2022 12:19:17 +0100 Message-ID: <20220927111922.3602838-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In today's edition of moving things around: The PCIe root port on PolarFire SoC is more part of the FPGA than of the Core Complex. It is located on the other side of the chip and, apart from its interrupts, most of its configuration is determined by the FPGA bitstream rather. This includes: - address translation in both directions - the addresses at which the config and data regions appear to the core complex - the clocks used by the AXI bus - the plic interrupt used Moving the PCIe node to the -fabric.dtsi makes it clearer than a singular configuration for root port is not correct & allows the base SoC dtsi to be more easily included. Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 32 +++++++++++++++++-- .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 30 ----------------- 3 files changed, 58 insertions(+), 33 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index eec5aba43436..688ef0fc5a64 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -37,8 +37,34 @@ fabric_clk1: fabric-clk1 { #clock-cells =3D <0>; clock-frequency =3D <125000000>; }; -}; =20 -&pcie { - dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi index 49380c428ec9..67303bc0e451 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -13,4 +13,33 @@ fabric_clk1: fabric-clk1 { #clock-cells =3D <0>; clock-frequency =3D <125000000>; }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 45e3cc659882..79fd8dfce96f 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -464,36 +464,6 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - pcie: pcie@2000000000 { - compatible =3D "microchip,pcie-host-1.0"; - #address-cells =3D <0x3>; - #interrupt-cells =3D <0x1>; - #size-cells =3D <0x2>; - device_type =3D "pci"; - reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names =3D "cfg", "apb"; - bus-range =3D <0x0 0x7f>; - interrupt-parent =3D <&plic>; - interrupts =3D <119>; - interrupt-map =3D <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask =3D <0 0 0 7>; - clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names =3D "fic0", "fic1", "fic3"; - ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; - msi-parent =3D <&pcie>; - msi-controller; - microchip,axi-m-atr0 =3D <0x10 0x0>; - status =3D "disabled"; - pcie_intc: legacy-interrupt-controller { - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - interrupt-controller; - }; - }; - mbox: mailbox@37020000 { compatible =3D "microchip,mpfs-mailbox"; reg =3D <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19C71C6FA8E for ; Tue, 27 Sep 2022 11:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231871AbiI0LVV (ORCPT ); Tue, 27 Sep 2022 07:21:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231292AbiI0LUZ (ORCPT ); Tue, 27 Sep 2022 07:20:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E27A34F6AE; Tue, 27 Sep 2022 04:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277623; x=1695813623; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lT0bVFe59r0LZtVlbhkUSjAZd0dwPCr+Kqah6r2WiU8=; b=Rkf630tSzgnH3UiXWkqMiopnFWtGAuPghs15K1W7xIKannd/KTKBDzbD 0l1x/2ExQCBA/9t26ZwL28S8lRJVmnZ0X7NurHdehJ1JOUnK5rCtDpcek ndLVoTzDo7i8ySzrOszn8bTltPFrRn1tri8XPGakDHh9WZCWLOAO1ZzJ2 NNpU/nc+OtJENQl2rMou1MGgEdmjbAwAHCVJqyoR3CbkY4znfwua+4hbc cwAAb0M15jc5j3gjI6gfuiRhYgNyIMvtljvku5k3CWpdCVdJFrL3o6P+9 cxerS+3BhLlTGU+58wPsG1oO7/Fxhd8vRYLhcF5U5nIf6DkK6W9V9oLiA w==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="179094369" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:23 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:14 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:11 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 06/11] riscv: dts: microchip: icicle: update pci address properties Date: Tue, 27 Sep 2022 12:19:18 +0100 Message-ID: <20220927111922.3602838-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 688ef0fc5a64..9ca2ac4ad8e2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -38,13 +38,13 @@ fabric_clk1: fabric-clk1 { clock-frequency =3D <125000000>; }; =20 - pcie: pcie@2000000000 { + pcie: pcie@3000000000 { compatible =3D "microchip,pcie-host-1.0"; #address-cells =3D <0x3>; #interrupt-cells =3D <0x1>; #size-cells =3D <0x2>; device_type =3D "pci"; - reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg =3D <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; reg-names =3D "cfg", "apb"; bus-range =3D <0x0 0x7f>; interrupt-parent =3D <&plic>; @@ -54,9 +54,9 @@ pcie: pcie@2000000000 { <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask =3D <0 0 0 7>; - clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names =3D "fic0", "fic1", "fic3"; - ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + clocks =3D <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; msi-parent =3D <&pcie>; msi-controller; --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80073C6FA82 for ; Tue, 27 Sep 2022 11:21:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232124AbiI0LV1 (ORCPT ); Tue, 27 Sep 2022 07:21:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231420AbiI0LUZ (ORCPT ); Tue, 27 Sep 2022 07:20:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5905857274; Tue, 27 Sep 2022 04:20:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277624; x=1695813624; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z5gQaoAmgcNsBt6UN6nHGaKgQKU1tky1WsEv+3dwAJA=; b=K1zhU3TvaNAJYQ/+n23KVCmdxRWT1/d1FevQeUcnGFtcL0mSuCG35ykW AoHoLwGVVrL+UUMoVpYA3oRhny2cAmkrVAHeGrSYUFfMncWAwHCHP+2v1 M1ftjjzJ9YWEaFS2RXY7zSQqzTSOeSdXUnRnxu+k9kweO+m9B9QR5UUyq CRLDGIgl2J4Kn4f+vOCbQmKFXFWTC/S9TZFvBtH8j5TidlOUdlR1h8XDO mkWCeFCDU8H/qVO/y2j9c/KrAhxSCB5qjADvIr5TErBr/3oeKUJ1DBg0e Q6DykQTfHEhL43NXFUAph9Jq8n+eGrS2bsi4Ng5cGqGc76vs0i4mp28mP w==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="179094371" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:23 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:17 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:14 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 07/11] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Date: Tue, 27 Sep 2022 12:19:19 +0100 Message-ID: <20220927111922.3602838-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When users try to add onto the reference design, they find that the current addresses that peripherals connected to Fabric InterConnect (FIC) 3 use are restrictive. For the v2022.09 reference design, the peripherals have been shifted down, leaving more contiguous address space for their custom IP/peripherals. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 9ca2ac4ad8e2..35030ea330ee 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -5,18 +5,18 @@ / { compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", "microchip,mpfs"; =20 - core_pwm0: pwm@41000000 { + core_pwm0: pwm@40000000 { compatible =3D "microchip,corepwm-rtl-v4"; - reg =3D <0x0 0x41000000 0x0 0xF0>; + reg =3D <0x0 0x40000000 0x0 0xF0>; microchip,sync-update-mask =3D /bits/ 32 <0>; #pwm-cells =3D <2>; clocks =3D <&fabric_clk3>; status =3D "disabled"; }; =20 - i2c2: i2c@44000000 { + i2c2: i2c@40000200 { compatible =3D "microchip,corei2c-rtl-v7"; - reg =3D <0x0 0x44000000 0x0 0x1000>; + reg =3D <0x0 0x40000200 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; clocks =3D <&fabric_clk3>; --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21BF0C6FA92 for ; Tue, 27 Sep 2022 11:21:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232128AbiI0LVg (ORCPT ); Tue, 27 Sep 2022 07:21:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231174AbiI0LU0 (ORCPT ); Tue, 27 Sep 2022 07:20:26 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A798151406; Tue, 27 Sep 2022 04:20:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277625; x=1695813625; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DtjFB323S4Wx5S1fAIRUAwQUn/ZVmDrcjqP1LgDfbcc=; b=DLyJM9l6Ts9zhUYd7iKywbUd2jC535RNe/duka/WX8SA+mk9UsM91KE7 7Rrj4WfDTgPhhx6yr59XeJPB1GAbPXZEaANBYavbmwzbI4y1md3tNf/ie 7tURFqJo4tIMgNm1M7UpgGiXVwQ2yFYc1+EzA11CKUus88Euv+bqP1maD 6DFqEPGdWAYz8Wj/I7xWKsmYlyqAs+fINjpnKZ0shaeQnsaXwSVJqb4Vs HE+OOCTCo/VawTJWCJVXLfEbseRtiIZVUzcuFoRLVEoRECZfZ+C6CWBJ3 IXU8Clmr/s7hXZj0W6B/taO1ODbKR/dNGCioFUVZsNpzG+KBd/hDYJ4Ty Q==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="179094376" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:24 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:20 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:17 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 08/11] riscv: dts: microchip: reduce the fic3 clock rate Date: Tue, 27 Sep 2022 12:19:20 +0100 Message-ID: <20220927111922.3602838-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For the v2022.09 release of the reference design, the fic3 clock rate been reduced from 62.5 MHz to 50 MHz as it allows timing to be closed significantly more quickly by customers who chose to build the reference design themselves. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 35030ea330ee..b6bfe177ccb2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -29,7 +29,7 @@ i2c2: i2c@40000200 { fabric_clk3: fabric-clk3 { compatible =3D "fixed-clock"; #clock-cells =3D <0>; - clock-frequency =3D <62500000>; + clock-frequency =3D <50000000>; }; =20 fabric_clk1: fabric-clk1 { --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D441C6FA8E for ; Tue, 27 Sep 2022 11:21:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232132AbiI0LVk (ORCPT ); Tue, 27 Sep 2022 07:21:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231642AbiI0LU2 (ORCPT ); Tue, 27 Sep 2022 07:20:28 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E6A954C84; Tue, 27 Sep 2022 04:20:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277626; x=1695813626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hEKnwwtNJPu/Lc90Ya+WHDXfcID2nQ42G1LiippA8aI=; b=a/lHNm9lugaE3n6r/HB7fYZPLOcbou56wNthppniPI5w1auoRdtGA0h9 5xLoh9YYDTRxu9O4k0KMnvGe1WOJs/UfUqBdwpeaV5iMmzGVMsEq0+3wa pUkdnlINhFk421ITUnxATQ7c+v9/MAu6TebFQLIpMF1MGecK5BMKqNn4G ejaqWq6ft/EoB2ofNI25INJdjJWNuWgTxphrnnWzTbuuNrNIiQQ0G8leV T6HL98xTL0KsJ1YPxMTQ11fLSSKNeAQP25tlwwiH2JGRPfHorSBwHUeKT nrtxBjXfEdzcO5hvbbtKC/Y6i2bT/fqahtrbUK616lJ346rPN25tXAayR g==; X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="179094388" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:22 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:20 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 09/11] riscv: dts: microchip: add sevkit device tree Date: Tue, 27 Sep 2022 12:19:21 +0100 Message-ID: <20220927111922.3602838-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vattipalli Praveen Add a basic dts for the Microchip Smart Embedded Vision dev kit. The SEV kit is an upcoming first party board, featuring an MPFS250T and: - Dual Sony Camera Sensors (IMX334) - IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi - Bluetooth 5 Low Energy - 4 GB DDR4 x64 - 2 GB LPDDR4 x32 - 1 GB SPI Flash - 8 GB eMMC flash & SD card slot (multiplexed) - HDMI2.0 Video Input/Output - MIPI DSI Output - MIPI CSI-2 Input Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77= E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Vattipalli Praveen Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 ++++++ .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++++++ 3 files changed, 191 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index 39aae7b04f1c..f18477b2e86d 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi b/arch/= riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi new file mode 100644 index 000000000000..8545baf4d129 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <0>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/bo= ot/dts/microchip/mpfs-sev-kit.dts new file mode 100644 index 000000000000..013cb666c72d --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-sev-kit-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "Microchip PolarFire-SoC SEV Kit"; + compatible =3D "microchip,mpfs-sev-kit", "microchip,mpfs"; + + aliases { + ethernet0 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + fabricbuf0ddrc: buffer@80000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x80000000 0x0 0x2000000>; + }; + + fabricbuf1ddrnc: buffer@c4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0xc4000000 0x0 0x4000000>; + }; + + fabricbuf2ddrncwcb: buffer@d4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0xd4000000 0x0 0x4000000>; + }; + }; + + ddrc_cache: memory@1000000000 { + device_type =3D "memory"; + reg =3D <0x10 0x0 0x0 0x76000000>; + }; +}; + +&i2c0 { + status =3D "okay"; +}; + +&gpio2 { + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status =3D "okay"; +}; + +&mac0 { + status =3D "okay"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; + phy1: ethernet-phy@9 { + reg =3D <9>; + }; + phy0: ethernet-phy@8 { + reg =3D <8>; + }; +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy1>; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + status =3D "okay"; + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "otg"; +}; --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F33BEC6FA82 for ; Tue, 27 Sep 2022 11:21:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231795AbiI0LVn (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="182238395" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Sep 2022 04:20:26 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 27 Sep 2022 04:20:25 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 27 Sep 2022 04:20:23 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 10/11] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Date: Tue, 27 Sep 2022 12:19:22 +0100 Message-ID: <20220927111922.3602838-11-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device trees for both configs used by the Aries Embedded M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM, featuring: - 2GB DDR4 SDRAM dedicated to the HMS - 512MB DDR4 SDRAM dedicated to the FPGA - 32 MB SPI NOR Flash - 4 GByte eMMC and a carrier board with: - 2x Gigabit Ethernet - USB - 2x UART - 2x CAN - TFT connector - HSMC extension connector - 3x PMOD extension connectors - microSD-card slot Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-s= om-mpfs025t-pcie-serdes Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchi= p-soc-fpga-m100pfsevp-riscv-hsmc-pmod Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFS= EVP-Schematics.pdf Co-developed-by: Wolfgang Grandegger Signed-off-by: Wolfgang Grandegger Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++ .../boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++ 3 files changed, 225 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index f18477b2e86d..7427a20934f3 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/= riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi new file mode 100644 index 000000000000..7b9ee13b6a3a --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv= /boot/dts/microchip/mpfs-m100pfsevp.dts new file mode 100644 index 000000000000..184cb36a175e --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-m100pfs-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model =3D "Aries Embedded M100PFEVPS"; + compatible =3D "aries,m100pfsevp", "microchip,mpfs"; + + aliases { + ethernet0 =3D &mac0; + ethernet1 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + gpio0 =3D &gpio0; + gpio1 =3D &gpio2; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x40000000>; + }; + ddrc_cache_hi: memory@1040000000 { + device_type =3D "memory"; + reg =3D <0x10 0x40000000 0x0 0x40000000>; + }; +}; + +&can0 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + +&gpio0 { + interrupts =3D <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>; + ngpios =3D <14>; + status =3D "okay"; + + pmic-irq-hog { + gpio-hog; + gpios =3D <13 0>; + input; + }; + + /* Set to low for eMMC, high for SD-card */ + mmc-sel-hog { + gpio-hog; + gpios =3D <12 0>; + output-high; + }; +}; + +&gpio2 { + interrupts =3D <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>, <27>, <28>, + <29>, <30>, <31>, <32>, + <33>, <34>, <35>, <36>, + <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>; + status =3D "okay"; +}; + +&mac0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy1>; + phy1: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + max-frequency =3D <50000000>; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + disable-wp; + status =3D "okay"; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&pcie { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "host"; +}; --=20 2.37.3 From nobody Tue Dec 16 11:09:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC333C6FA82 for ; Tue, 27 Sep 2022 11:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232133AbiI0LVt (ORCPT ); Tue, 27 Sep 2022 07:21:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230388AbiI0LUb (ORCPT ); Tue, 27 Sep 2022 07:20:31 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 649DC100; Tue, 27 Sep 2022 04:20:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1664277629; 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Tue, 27 Sep 2022 04:20:26 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v6 11/11] riscv: dts: microchip: update memory configuration for v2022.10 Date: Tue, 27 Sep 2022 12:19:23 +0100 Message-ID: <20220927111922.3602838-12-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com> References: <20220927111922.3602838-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the v2022.10 reference design, the seg registers are going to be changed, resulting in a required change to the memory map in Linux. A small 4M reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, so that it can cache its payload.bin between reboots of a specific context. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index 42d350fe6c6b..31f88cb4d5e5 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -33,15 +33,26 @@ cpus { =20 ddrc_cache_lo: memory@80000000 { device_type =3D "memory"; - reg =3D <0x0 0x80000000 0x0 0x2e000000>; + reg =3D <0x0 0x80000000 0x0 0x40000000>; status =3D "okay"; }; =20 ddrc_cache_hi: memory@1000000000 { device_type =3D "memory"; - reg =3D <0x10 0x0 0x0 0x40000000>; + reg =3D <0x10 0x40000000 0x0 0x40000000>; status =3D "okay"; }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hss_payload: region@BFC00000 { + reg =3D <0x0 0xBFC00000 0x0 0x400000>; + no-map; + }; + }; }; =20 &core_pwm0 { --=20 2.37.3