This adds the thermal zone for the mt8195.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Ben Tseng <ben.tseng@mediatek.com>
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 115 ++++++++++++++++++++++-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 4fbf24b5d202..78017224930c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
- * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2022 MediaTek Inc.
* Author: Seiya Wang <seiya.wang@mediatek.com>
*/
@@ -11,6 +11,9 @@
#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "mediatek,mt8195";
@@ -810,6 +813,28 @@ spi0: spi@1100a000 {
status = "disabled";
};
+ lvtsap: thermal-sensor@1100b000 {
+ compatible = "mediatek,mt8195-lvts-ap";
+ #thermal-sensor-cells = <1>;
+ reg = <0 0x1100b000 0 0x400>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+ resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
+ nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
+ nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2";
+ };
+
+ lvtsmcu: thermal-sensor@11278000 {
+ compatible = "mediatek,mt8195-lvts-mcu";
+ #thermal-sensor-cells = <1>;
+ reg = <0 0x11278000 0 0x400>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+ resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
+ nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
+ nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2";
+ };
+
spi1: spi@11010000 {
compatible = "mediatek,mt8195-spi",
"mediatek,mt6765-spi";
@@ -1613,4 +1638,92 @@ vencsys_core1: clock-controller@1b000000 {
#clock-cells = <1>;
};
};
+
+ thermal_zones: thermal-zones {
+ cpu-big1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsmcu 0>;
+ };
+ cpu-big2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsmcu 1>;
+ };
+ cpu-big3-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsmcu 2>;
+ };
+ cpu-big4-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsmcu 3>;
+ };
+ cpu-little1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsmcu 4>;
+ };
+ cpu-little2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsmcu 5>;
+ };
+ cpu-little3-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsmcu 6>;
+ };
+ cpu-little4-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsmcu 7>;
+ };
+ vpu1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsap 0>;
+ };
+ vpu2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsap 1>;
+ };
+ gpu1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsap 2>;
+ };
+ gpu2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsap 3>;
+ };
+ vdec-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsap 4>;
+ };
+ img-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsap 5>;
+ };
+ infra-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsap 6>;
+ };
+ cam1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsap 7>;
+ };
+ cam2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvtsap 8>;
+ };
+ };
};
--
2.34.1
On Tue, Jul 26, 2022 at 03:55:06PM +0200, Balsam CHIHI wrote: > This adds the thermal zone for the mt8195. > > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > Signed-off-by: Ben Tseng <ben.tseng@mediatek.com> > Signed-off-by: Alexandre Bailon <abailon@baylibre.com> > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 115 ++++++++++++++++++++++- > 1 file changed, 114 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 4fbf24b5d202..78017224930c 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: (GPL-2.0 OR MIT) > /* > - * Copyright (c) 2021 MediaTek Inc. > + * Copyright (c) 2022 MediaTek Inc. > * Author: Seiya Wang <seiya.wang@mediatek.com> > */ > > @@ -11,6 +11,9 @@ > #include <dt-bindings/memory/mt8195-memory-port.h> > #include <dt-bindings/phy/phy.h> > #include <dt-bindings/pinctrl/mt8195-pinfunc.h> > +#include <dt-bindings/power/mt8195-power.h> > +#include <dt-bindings/reset/mt8195-resets.h> > +#include <dt-bindings/thermal/thermal.h> You're not actually using the mt8195-power and thermal includes. > > / { > compatible = "mediatek,mt8195"; > @@ -810,6 +813,28 @@ spi0: spi@1100a000 { > status = "disabled"; > }; > > + lvtsap: thermal-sensor@1100b000 { Can you name this label lvts_ap, and the one below lvts_mcu, please? Makes it much more readable. > + compatible = "mediatek,mt8195-lvts-ap"; > + #thermal-sensor-cells = <1>; > + reg = <0 0x1100b000 0 0x400>; Don't you need the reg size to be 0x1000 to be able to access THERMINTST in the soc_temp_lvts.c? > + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; > + resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; > + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; > + nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2"; > + }; > + > + lvtsmcu: thermal-sensor@11278000 { > + compatible = "mediatek,mt8195-lvts-mcu"; > + #thermal-sensor-cells = <1>; > + reg = <0 0x11278000 0 0x400>; > + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; > + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; > + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; > + nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2"; > + }; > + > spi1: spi@11010000 { > compatible = "mediatek,mt8195-spi", > "mediatek,mt6765-spi"; > @@ -1613,4 +1638,92 @@ vencsys_core1: clock-controller@1b000000 { > #clock-cells = <1>; > }; > }; > + > + thermal_zones: thermal-zones { > + cpu-big1-thermal { > + polling-delay = <0>; /* milliseconds */ > + polling-delay-passive = <0>; /* milliseconds */ Please drop all these '/* milliseconds */' comments. The thermal-zones dt-binding already defines both of these properties as being in milliseconds, so this is just polluting the DT. Thanks, Nícolas
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