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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id d13-20020adf9c8d000000b0021e4c3b2967sm15244670wre.65.2022.07.26.06.55.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 06:55:22 -0700 (PDT) From: Balsam CHIHI To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v8 6/6] arm64: dts: mt8195: Add thermal zone Date: Tue, 26 Jul 2022 15:55:06 +0200 Message-Id: <20220726135506.485108-7-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726135506.485108-1-bchihi@baylibre.com> References: <20220726135506.485108-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the thermal zone for the mt8195. Signed-off-by: Tinghan Shen Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 115 ++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 4fbf24b5d202..78017224930c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* - * Copyright (c) 2021 MediaTek Inc. + * Copyright (c) 2022 MediaTek Inc. * Author: Seiya Wang */ =20 @@ -11,6 +11,9 @@ #include #include #include +#include +#include +#include =20 / { compatible =3D "mediatek,mt8195"; @@ -810,6 +813,28 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvtsap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8195-lvts-ap"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x1100b000 0 0x400>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells =3D <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names =3D "lvts_calib_data1", "lvts_calib_data2"; + }; + + lvtsmcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8195-lvts-mcu"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x11278000 0 0x400>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names =3D "lvts_calib_data1", "lvts_calib_data2"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -1613,4 +1638,92 @@ vencsys_core1: clock-controller@1b000000 { #clock-cells =3D <1>; }; }; + + thermal_zones: thermal-zones { + cpu-big1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 0>; + }; + cpu-big2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 1>; + }; + cpu-big3-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 2>; + }; + cpu-big4-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 3>; + }; + cpu-little1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 4>; + }; + cpu-little2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 5>; + }; + cpu-little3-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 6>; + }; + cpu-little4-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 7>; + }; + vpu1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 0>; + }; + vpu2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 1>; + }; + gpu1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 2>; + }; + gpu2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 3>; + }; + vdec-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 4>; + }; + img-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 5>; + }; + infra-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 6>; + }; + cam1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 7>; + }; + cam2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 8>; + }; + }; }; --=20 2.34.1