Enable MT8192's PCIe controller and add support for the MT7921e WiFi
card that is present on that bus for the Asurada platform.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v3)

Changes in v3:
- Renamed regulator node to be generic

Changes in v2:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 69bb43f7b346..e59c178d3d26 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -66,6 +66,19 @@ pp3300_u: regulator-3v3-u {
 		vin-supply = <&pp3300_g>;
 	};
 
+	pp3300_wlan: regulator-3v3-wlan {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_wlan";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pp3300_wlan_pins>;
+		enable-active-high;
+		gpio = <&pio 143 GPIO_ACTIVE_HIGH>;
+	};
+
 	/* system wide switching 5.0V power rail */
 	pp5000_a: regulator-5v0-a {
 		compatible = "regulator-fixed";
@@ -84,6 +97,17 @@ ppvar_sys: regulator-var-sys {
 		regulator-always-on;
 		regulator-boot-on;
 	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi_restricted_dma_region: wifi@c0000000 {
+			compatible = "restricted-dma-pool";
+			reg = <0 0xc0000000 0 0x4000000>;
+		};
+	};
 };
 
 &i2c0 {
@@ -144,6 +168,28 @@ &i2c7 {
 	pinctrl-0 = <&i2c7_pins>;
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+
+	pcie0: pcie@0,0 {
+		device_type = "pci";
+		reg = <0x0000 0 0 0 0>;
+		num-lanes = <1>;
+		bus-range = <0x1 0x1>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi: wifi@0,0 {
+			reg = <0x10000 0 0 0 0x100000>,
+			      <0x10000 0 0x100000 0 0x100000>;
+			memory-region = <&wifi_restricted_dma_region>;
+		};
+	};
+};
+
 &pio {
 	/* 220 lines */
 	gpio-line-names = "I2S_DP_LRCK",
@@ -430,6 +476,34 @@ pins-bus {
 		};
 	};
 
+	pcie_pins: pcie-default-pins {
+		pins-pcie-wake {
+			pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
+			bias-pull-up;
+		};
+
+		pins-pcie-pereset {
+			pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>;
+		};
+
+		pins-pcie-clkreq {
+			pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>;
+			bias-pull-up;
+		};
+
+		pins-wifi-kill {
+			pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */
+			output-high;
+		};
+	};
+
+	pp3300_wlan_pins: pp3300-wlan-pins {
+		pins-pcie-en-pp3300-wlan {
+			pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
+			output-high;
+		};
+	};
+
 	spi1_pins: spi1-default-pins {
 		pins-cs-mosi-clk {
 			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
-- 
2.36.1

On Wed, Jun 29, 2022 at 11:59:51AM -0400, Nícolas F. R. A. Prado wrote:
> Enable MT8192's PCIe controller and add support for the MT7921e WiFi
> card that is present on that bus for the Asurada platform.

> +&pcie {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie_pins>;
> +
> +	pcie0: pcie@0,0 {
> +		device_type = "pci";
> +		reg = <0x0000 0 0 0 0>;
> +		num-lanes = <1>;
> +		bus-range = <0x1 0x1>;

Hi Nícolas, what's the purpose of this bus-range?  IIUC this describes
a Root Port, where we can read and configure the secondary/subordinate
bus numbers from the RP config space, so it seems like we don't need
to describe them here.

> +
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		wifi: wifi@0,0 {
> +			reg = <0x10000 0 0 0 0x100000>,
> +			      <0x10000 0 0x100000 0 0x100000>;
> +			memory-region = <&wifi_restricted_dma_region>;
> +		};
> +	};
> +};

On Fri, Jan 03, 2025 at 03:14:46PM -0600, Bjorn Helgaas wrote:
> On Wed, Jun 29, 2022 at 11:59:51AM -0400, Nícolas F. R. A. Prado wrote:
> > Enable MT8192's PCIe controller and add support for the MT7921e WiFi
> > card that is present on that bus for the Asurada platform.
> 
> > +&pcie {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pcie_pins>;
> > +
> > +	pcie0: pcie@0,0 {
> > +		device_type = "pci";
> > +		reg = <0x0000 0 0 0 0>;
> > +		num-lanes = <1>;
> > +		bus-range = <0x1 0x1>;
> 
> Hi Nícolas, what's the purpose of this bus-range?  IIUC this describes
> a Root Port, where we can read and configure the secondary/subordinate
> bus numbers from the RP config space, so it seems like we don't need
> to describe them here.

Hi Bjorn,

that was carried over from the downstream sources. I just tried removing it and
indeed I don't see any difference in the PCI log messages, or the bus number,
and the wifi works just fine. I can send a follow up patch removing it.

Thanks,
Nícolas

[+cc Mani]

On Mon, Jan 06, 2025 at 04:10:32PM -0300, Nícolas F. R. A. Prado wrote:
> On Fri, Jan 03, 2025 at 03:14:46PM -0600, Bjorn Helgaas wrote:
> > On Wed, Jun 29, 2022 at 11:59:51AM -0400, Nícolas F. R. A. Prado wrote:
> > > Enable MT8192's PCIe controller and add support for the MT7921e WiFi
> > > card that is present on that bus for the Asurada platform.
> > 
> > > +&pcie {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pcie_pins>;
> > > +
> > > +	pcie0: pcie@0,0 {
> > > +		device_type = "pci";
> > > +		reg = <0x0000 0 0 0 0>;
> > > +		num-lanes = <1>;
> > > +		bus-range = <0x1 0x1>;
> > 
> > Hi Nícolas, what's the purpose of this bus-range?  IIUC this describes
> > a Root Port, where we can read and configure the secondary/subordinate
> > bus numbers from the RP config space, so it seems like we don't need
> > to describe them here.
> 
> Hi Bjorn,
> 
> that was carried over from the downstream sources. I just tried
> removing it and indeed I don't see any difference in the PCI log
> messages, or the bus number, and the wifi works just fine. I can
> send a follow up patch removing it.

There might be a DTC check issue if we remove the bus-range:
https://lore.kernel.org/r/20250105101612.t6c4pw5uxhb5rdde@thinkpad

We might need to figure out how to resolve that first.

Bjorn

On Mon, Jan 06, 2025 at 02:56:07PM -0600, Bjorn Helgaas wrote:
> [+cc Mani]
> 
> On Mon, Jan 06, 2025 at 04:10:32PM -0300, Nícolas F. R. A. Prado wrote:
> > On Fri, Jan 03, 2025 at 03:14:46PM -0600, Bjorn Helgaas wrote:
> > > On Wed, Jun 29, 2022 at 11:59:51AM -0400, Nícolas F. R. A. Prado wrote:
> > > > Enable MT8192's PCIe controller and add support for the MT7921e WiFi
> > > > card that is present on that bus for the Asurada platform.
> > > 
> > > > +&pcie {
> > > > +	pinctrl-names = "default";
> > > > +	pinctrl-0 = <&pcie_pins>;
> > > > +
> > > > +	pcie0: pcie@0,0 {
> > > > +		device_type = "pci";
> > > > +		reg = <0x0000 0 0 0 0>;
> > > > +		num-lanes = <1>;
> > > > +		bus-range = <0x1 0x1>;
> > > 
> > > Hi Nícolas, what's the purpose of this bus-range?  IIUC this describes
> > > a Root Port, where we can read and configure the secondary/subordinate
> > > bus numbers from the RP config space, so it seems like we don't need
> > > to describe them here.
> > 
> > Hi Bjorn,
> > 
> > that was carried over from the downstream sources. I just tried
> > removing it and indeed I don't see any difference in the PCI log
> > messages, or the bus number, and the wifi works just fine. I can
> > send a follow up patch removing it.
> 
> There might be a DTC check issue if we remove the bus-range:
> https://lore.kernel.org/r/20250105101612.t6c4pw5uxhb5rdde@thinkpad

Ah yes, indeed there is:

arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi:643.18-647.5: Warning (pci_device_bus_num): /soc/pcie@11230000/pcie@0,0/wifi@0,0: PCI bus number 1 out of range, expected (0 - 0)

Thanks,
Nícolas

> 
> We might need to figure out how to resolve that first.
> 
> Bjorn