[v5] Add support for Xilinx Versal CPM5 Root Port

[PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port

Bharat Kumar Gogada posted 2 patches 3 years, 10 months ago

Diff against v1 v1 v2 v3 v4 v5 v5 v6
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There is a newer version of this series

.../bindings/pci/xilinx-versal-cpm.yaml       | 48 ++++++++++++--
drivers/pci/controller/pcie-xilinx-cpm.c      | 62 ++++++++++++++++++-
2 files changed, 103 insertions(+), 7 deletions(-)

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[PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port

Posted by Bharat Kumar Gogada 3 years, 10 months ago

Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
  to enable and handle legacy interrupts.

Changes in v5:
- Added of_device_get_match_data to identify CPM version.


Bharat Kumar Gogada (2):
  dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

 .../bindings/pci/xilinx-versal-cpm.yaml       | 48 ++++++++++++--
 drivers/pci/controller/pcie-xilinx-cpm.c      | 62 ++++++++++++++++++-
 2 files changed, 103 insertions(+), 7 deletions(-)

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2.17.1