Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additional register bit
  to enable and handle legacy interrupts.

Changes in v6:
- Added of_device_get_match_data to identify CPM version.
- Used enum values to differentiate CPM version.

Bharat Kumar Gogada (2):
  dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

 .../bindings/pci/xilinx-versal-cpm.yaml       | 38 ++++++++++-
 drivers/pci/controller/pcie-xilinx-cpm.c      | 64 ++++++++++++++++++-
 2 files changed, 98 insertions(+), 4 deletions(-)

-- 
2.17.1

On Tue, Jul 05, 2022 at 04:26:44PM +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functioning at Gen5 speed.
> 
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additional register bit
>   to enable and handle legacy interrupts.
> 
> Changes in v6:
> - Added of_device_get_match_data to identify CPM version.
> - Used enum values to differentiate CPM version.
> 
> Bharat Kumar Gogada (2):
>   dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
>   PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
> 
>  .../bindings/pci/xilinx-versal-cpm.yaml       | 38 ++++++++++-
>  drivers/pci/controller/pcie-xilinx-cpm.c      | 64 ++++++++++++++++++-
>  2 files changed, 98 insertions(+), 4 deletions(-)

Applied to pci/ctrl/xilinx-cpm for v5.20, thanks!

I tweaked the driver patch to test:

  if (port->variant->version == CPM5)

instead of just:

  if (port->variant->version)

so it doesn't depend on the enum values.

Thanks Bjorn. 

> On Tue, Jul 05, 2022 at 04:26:44PM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root Port
> > functioning at Gen5 speed.
> >
> > Xilinx Versal CPM5 has few changes with existing CPM block.
> > - CPM5 has dedicated register space for control and status registers.
> > - CPM5 legacy interrupt handling needs additional register bit
> >   to enable and handle legacy interrupts.
> >
> > Changes in v6:
> > - Added of_device_get_match_data to identify CPM version.
> > - Used enum values to differentiate CPM version.
> >
> > Bharat Kumar Gogada (2):
> >   dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
> >   PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
> >
> >  .../bindings/pci/xilinx-versal-cpm.yaml       | 38 ++++++++++-
> >  drivers/pci/controller/pcie-xilinx-cpm.c      | 64 ++++++++++++++++++-
> >  2 files changed, 98 insertions(+), 4 deletions(-)
> 
> Applied to pci/ctrl/xilinx-cpm for v5.20, thanks!
> 
> I tweaked the driver patch to test:
> 
>   if (port->variant->version == CPM5)
> 
> instead of just:
> 
>   if (port->variant->version)
> 
> so it doesn't depend on the enum values.

Ping!

> -----Original Message-----
> From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> Sent: Tuesday, July 5, 2022 4:27 PM
> To: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: bhelgaas@google.com; michals@xilinx.com; Bharat Kumar Gogada
> <bharat.kumar.gogada@xilinx.com>
> Subject: [PATCH v6 0/2] Add support for Xilinx Versal CPM5 Root Port
> 
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functioning at Gen5 speed.
> 
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additional register bit
>   to enable and handle legacy interrupts.
> 
> Changes in v6:
> - Added of_device_get_match_data to identify CPM version.
> - Used enum values to differentiate CPM version.
> 
> Bharat Kumar Gogada (2):
>   dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
>   PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
> 
>  .../bindings/pci/xilinx-versal-cpm.yaml       | 38 ++++++++++-
>  drivers/pci/controller/pcie-xilinx-cpm.c      | 64 ++++++++++++++++++-
>  2 files changed, 98 insertions(+), 4 deletions(-)
> 
> --
> 2.17.1