[v1] Add support for Xilinx Versal CPM5 Root Port

[PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port

Bharat Kumar Gogada posted 2 patches 4 years, 4 months ago

Diff against v1 v2 v3 v4 v5 v5 v5 v6
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.../bindings/pci/xilinx-versal-cpm.yaml       | 47 ++++++++++++++++---
drivers/pci/controller/pcie-xilinx-cpm.c      | 33 ++++++++++++-
2 files changed, 72 insertions(+), 8 deletions(-)

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[PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port

Posted by Bharat Kumar Gogada 4 years, 4 months ago

Xilinx Versal Premium series has CPM5 block which supports Root port
functioning at Gen5 speed.
Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
  to enable and handle legacy interrupts.

Bharat Kumar Gogada (2):
  PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver

 .../bindings/pci/xilinx-versal-cpm.yaml       | 47 ++++++++++++++++---
 drivers/pci/controller/pcie-xilinx-cpm.c      | 33 ++++++++++++-
 2 files changed, 72 insertions(+), 8 deletions(-)

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2.17.1