This patch adds the device tree support for the XiangShan platform's nanhu soc

Signed-off-by: qinshaoqing <qinshaoqing@bosc.ac.cn>
---
 arch/riscv/Kconfig.socs                     |   5 +
 arch/riscv/boot/dts/Makefile                |   1 +
 arch/riscv/boot/dts/xiangshan/Makefile      |   2 +
 arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts | 226 ++++++++++++++++++++
 4 files changed, 234 insertions(+)
 create mode 100644 arch/riscv/boot/dts/xiangshan/Makefile
 create mode 100644 arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index f51bb24bc84c..89c80fd493fb 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -80,4 +80,9 @@ config SOC_CANAAN_K210
  help
    This enables support for Canaan Kendryte K210 SoC platform hardware.

+config SOC_XIANGSHAN
+        bool "XiangShan SoCs"
+        help
+          This enables support for XiangShan SoC platform hardware
+
 endmenu # "SoC selection"
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index fdae05bbf556..43a79cc9dd7c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -7,5 +7,6 @@ subdir-y += sifive
 subdir-y += sophgo
 subdir-y += starfive
 subdir-y += thead
+subdir-y += xiangshan

 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE))
diff --git a/arch/riscv/boot/dts/xiangshan/Makefile b/arch/riscv/boot/dts/xiangshan/Makefile
new file mode 100644
index 000000000000..41e585490a97
--- /dev/null
+++ b/arch/riscv/boot/dts/xiangshan/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_XIANGSHAN) += nanhu-v3a.dtb
diff --git a/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts b/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts
new file mode 100644
index 000000000000..560de7c7f22e
--- /dev/null
+++ b/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2024-2025 BOSC */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "bosc,nanhu-v3a";
+
+ cpus {
+  #address-cells = <1>;
+  #size-cells = <0>;
+  timebase-frequency = <24000000>;
+
+  cpu0: cpu@0 {
+   compatible = "bosc,nanhu-v3a", "riscv";
+   device_type = "cpu";
+   riscv,isa = "rv64imafdcv";
+   d-cache-block-size = <64>;
+   d-cache-sets = <64>;
+   d-cache-size = <16384>;
+   d-tlb-sets = <1>;
+   d-tlb-size = <32>;
+   i-cache-block-size = <64>;
+   i-cache-sets = <64>;
+   i-cache-size = <16384>;
+   i-tlb-sets = <1>;
+   i-tlb-size = <32>;
+   mmu-type = "riscv,sv39";
+   reg = <0x0>;
+
+   cpu0_intc: interrupt-controller {
+    #interrupt-cells = <1>;
+    compatible = "riscv,cpu-intc";
+    interrupt-controller;
+   };
+  };
+
+  cpu1: cpu@1 {
+   compatible = "bosc,nanhu-v3a", "riscv";
+   device_type = "cpu";
+   riscv,isa = "rv64imafdcv";
+   d-cache-block-size = <64>;
+   d-cache-sets = <64>;
+   d-cache-size = <16384>;
+   d-tlb-sets = <1>;
+   d-tlb-size = <32>;
+   i-cache-block-size = <64>;
+   i-cache-sets = <64>;
+   i-cache-size = <16384>;
+   i-tlb-sets = <1>;
+   i-tlb-size = <32>;
+   mmu-type = "riscv,sv39";
+   reg = <0x1>;
+
+   cpu1_intc: interrupt-controller {
+    #interrupt-cells = <1>;
+    compatible = "riscv,cpu-intc";
+    interrupt-controller;
+   };
+  };
+ };
+
+ clkc: misc_clk {
+  compatible = "fixed-clock";
+  #clock-cells = <0>;
+  clock-output-names = "clkc";
+  clock-frequency = <100000000>;
+ };
+
+ sdhci_clock: sdhci_clck {
+  compatible = "fixed-clock";
+  #clock-cells = <0>;
+  clock-output-names = "sdhci_clock";
+  clock-frequency = <25000000>;
+ };
+
+ i2c0_clock: i2c0_clck {
+  compatible = "fixed-clock";
+  #clock-cells = <0>;
+  clock-output-names = "i2c0_clock";
+  clock-frequency = <100000000>;
+ };
+
+ soc {
+  #address-cells = <2>;
+  #size-cells = <2>;
+  compatible = "bosc,nanhu-v3a-soc", "simple-bus";
+  ranges;
+
+  clint0: clint@38000000 {
+   compatible = "riscv,clint0";
+   interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7>;
+   reg = <0x0 0x38000000 0x0 0x10000>;
+   reg-names = "control";
+   clock-frequency-mhz = <10>;
+  };
+
+  plic: interrupt-controller@3c000000 {
+   #interrupt-cells = <1>;
+   compatible = "riscv,plic0";
+   interrupt-controller;
+   interrupts-extended = <&cpu0_intc 0xb &cpu0_intc 0x9 &cpu1_intc 0xb &cpu1_intc 0x9>;
+   reg = <0 0x3c000000 0 0x4000000>;
+   reg-names = "control";
+   riscv,max-priority = <7>;
+   riscv,ndev = <128>;
+  };
+
+  ethernet0: ethernet@190000 {
+   compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+   reg = <0 0x190000 0 0x10000>;
+   reg-names = "stmmaceth";
+   interrupt-parent = <&plic>;
+   interrupts = <76 75 74>;
+   interrupt-names = "eth_lpi", "macirq", "eth_wake_irq";
+   clock-names = "stmmaceth";
+   clocks = <&clkc>;
+   snps,pbl = <2>;
+   snps,mixed-burst;
+   phy-mode = "rgmii";
+   phy-handle = <&phy0>;
+   mdio0: mdio {
+    #address-cells = <0x1>;
+    #size-cells = <0x0>;
+    compatible = "snps,dwmac-mdio";
+    phy0: phy@0 {
+     phyaddr = <0x0>;
+     compatible = "marvell,88E1510";
+     device_type = "ethernet-phy";
+     reg = <0x0>;
+    };
+    phy1: phy@1 {
+     phyaddr = <0x1>;
+     compatible = "marvell,88E1510";
+     device_type = "ethernet-phy";
+     reg = <0x1>;
+    };
+   };
+  };
+
+  ethernet1: ethernet@1a0000 {
+   compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+   reg = <0 0x1a0000 0 0x10000>;
+   reg-names = "stmmaceth1";
+   interrupt-parent = <&plic>;
+   interrupts = <73 72 71>;
+   interrupt-names = "eth_lpi", "macirq", "eth_wake_irq";
+   clock-names = "stmmaceth";
+   clocks = <&clkc>;
+   snps,pbl = <2>;
+   snps,mixed-burst;
+   phy-mode = "rgmii";
+   fixed-link{
+    speed =  <1000>;
+    full-duplex;
+    pause;
+    asym-pause;
+   };
+  };
+
+  sdhci2: sdhci@1200000 {
+   compatible = "snps,dwcmshc-sdhci";
+   reg = <0 0x1200000 0 0x20000>;
+   interrupt-parent = <&plic>;
+   interrupts = <77 78>;
+   clocks = <&sdhci_clock>;
+   clock-names = "core";
+   no-1-8-v;
+   disable-wp;
+   bus-width = <4>;
+   max_req_size = <4096>;
+   status = "okay";
+  };
+
+  i2c@70000 {
+   compatible = "snps,designware-i2c";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x70000 0x0 0x10000>;
+   interrupts = <66>;
+   interrupt-parent = <&plic>;
+   clock-frequency = <100000>;
+   clocks = <&i2c0_clock>;
+   status = "okay";
+  };
+
+  i2c@80000 {
+   compatible = "snps,designware-i2c";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x80000 0x0 0x10000>;
+   interrupts = <65>;
+   interrupt-parent = <&plic>;
+   clock-frequency = <100000>;
+   clocks = <&i2c0_clock>;
+   status = "okay";
+  };
+
+  uart0: serial@50000 {
+   compatible = "ns16550a";
+   reg = <0x0 0x50000 0x0 0x10000>;
+   reg-shift = <0x02>;
+   reg-io-width = <0x04>;
+   interrupt-parent = <&plic>;
+   interrupts = <68>;
+   clock-frequency = <100000000>;
+   status = "okay";
+  };
+ };
+
+ memory: memory@100000000 {
+  device_type = "memory";
+  reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ aliases {
+  serial0 = &uart0;
+ };
+
+ chosen {
+  bootargs = "console=ttyS0,115200 earlycon";
+  stdout-path = "serial0:115200n8";
+ };
+};
--
2.43.0

On 17/07/2025 04:36, 秦少青 wrote:
> 
> 
> This patch adds the device tree support for the XiangShan platform's nanhu soc

Please read submitting patches document. It will also tell you which
tools you must also run.

> 
> Signed-off-by: qinshaoqing <qinshaoqing@bosc.ac.cn>
> ---
>  arch/riscv/Kconfig.socs                     |   5 +
>  arch/riscv/boot/dts/Makefile                |   1 +
>  arch/riscv/boot/dts/xiangshan/Makefile      |   2 +
>  arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts | 226 ++++++++++++++++++++
>  4 files changed, 234 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/xiangshan/Makefile
>  create mode 100644 arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index f51bb24bc84c..89c80fd493fb 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,9 @@ config SOC_CANAAN_K210
>   help
>     This enables support for Canaan Kendryte K210 SoC platform hardware.
> 
> +config SOC_XIANGSHAN
> +        bool "XiangShan SoCs"
> +        help
> +          This enables support for XiangShan SoC platform hardware
> +
>  endmenu # "SoC selection"
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index fdae05bbf556..43a79cc9dd7c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -7,5 +7,6 @@ subdir-y += sifive
>  subdir-y += sophgo
>  subdir-y += starfive
>  subdir-y += thead
> +subdir-y += xiangshan
> 
>  obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE))
> diff --git a/arch/riscv/boot/dts/xiangshan/Makefile b/arch/riscv/boot/dts/xiangshan/Makefile
> new file mode 100644
> index 000000000000..41e585490a97
> --- /dev/null
> +++ b/arch/riscv/boot/dts/xiangshan/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_XIANGSHAN) += nanhu-v3a.dtb
> diff --git a/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts b/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts
> new file mode 100644
> index 000000000000..560de7c7f22e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts
> @@ -0,0 +1,226 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2024-2025 BOSC */
> +
> +/dts-v1/;
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "bosc,nanhu-v3a";


Please follow kernel and DTS coding style.

Once you fix all the warnings, please paste dtbs_check W=1 report.

Best regards,
Krzysztof