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charset="utf-8" This patch adds the device tree support for the XiangShan platform's nanhu = soc Signed-off-by: qinshaoqing --- arch/riscv/Kconfig.socs =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 | =C2=A0 5 + arch/riscv/boot/dts/Makefile=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | =C2=A0 1 + arch/riscv/boot/dts/xiangshan/Makefile=C2=A0 =C2=A0 =C2=A0 | =C2=A0 2 + arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts | 226 ++++++++++++++++++++ 4 files changed, 234 insertions(+) create mode 100644 arch/riscv/boot/dts/xiangshan/Makefile create mode 100644 arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index f51bb24bc84c..89c80fd493fb 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -80,4 +80,9 @@ config SOC_CANAAN_K210 =C2=A0 help =C2=A0 =C2=A0 This enables support for Canaan Kendryte K210 SoC platform ha= rdware. +config SOC_XIANGSHAN +=C2=A0 =C2=A0 =C2=A0 =C2=A0 bool "XiangShan SoCs" +=C2=A0 =C2=A0 =C2=A0 =C2=A0 help +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 This enables support for XiangShan SoC = platform hardware + endmenu # "SoC selection" diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index fdae05bbf556..43a79cc9dd7c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -7,5 +7,6 @@ subdir-y +=3D sifive subdir-y +=3D sophgo subdir-y +=3D starfive subdir-y +=3D thead +subdir-y +=3D xiangshan obj-$(CONFIG_BUILTIN_DTB) :=3D $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SO= URCE)) diff --git a/arch/riscv/boot/dts/xiangshan/Makefile b/arch/riscv/boot/dts/x= iangshan/Makefile new file mode 100644 index 000000000000..41e585490a97 --- /dev/null +++ b/arch/riscv/boot/dts/xiangshan/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_XIANGSHAN) +=3D nanhu-v3a.dtb diff --git a/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts b/arch/riscv/boot/= dts/xiangshan/nanhu-v3a.dts new file mode 100644 index 000000000000..560de7c7f22e --- /dev/null +++ b/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2024-2025 BOSC */ + +/dts-v1/; + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "bosc,nanhu-v3a"; + + cpus { +=C2=A0 #address-cells =3D <1>; +=C2=A0 #size-cells =3D <0>; +=C2=A0 timebase-frequency =3D <24000000>; + +=C2=A0 cpu0: cpu@0 { + =C2=A0 compatible =3D "bosc,nanhu-v3a", "riscv"; + =C2=A0 device_type =3D "cpu"; + =C2=A0 riscv,isa =3D "rv64imafdcv"; + =C2=A0 d-cache-block-size =3D <64>; + =C2=A0 d-cache-sets =3D <64>; + =C2=A0 d-cache-size =3D <16384>; + =C2=A0 d-tlb-sets =3D <1>; + =C2=A0 d-tlb-size =3D <32>; + =C2=A0 i-cache-block-size =3D <64>; + =C2=A0 i-cache-sets =3D <64>; + =C2=A0 i-cache-size =3D <16384>; + =C2=A0 i-tlb-sets =3D <1>; + =C2=A0 i-tlb-size =3D <32>; + =C2=A0 mmu-type =3D "riscv,sv39"; + =C2=A0 reg =3D <0x0>; + + =C2=A0 cpu0_intc: interrupt-controller { +=C2=A0 =C2=A0 #interrupt-cells =3D <1>; +=C2=A0 =C2=A0 compatible =3D "riscv,cpu-intc"; +=C2=A0 =C2=A0 interrupt-controller; + =C2=A0 }; +=C2=A0 }; + +=C2=A0 cpu1: cpu@1 { + =C2=A0 compatible =3D "bosc,nanhu-v3a", "riscv"; + =C2=A0 device_type =3D "cpu"; + =C2=A0 riscv,isa =3D "rv64imafdcv"; + =C2=A0 d-cache-block-size =3D <64>; + =C2=A0 d-cache-sets =3D <64>; + =C2=A0 d-cache-size =3D <16384>; + =C2=A0 d-tlb-sets =3D <1>; + =C2=A0 d-tlb-size =3D <32>; + =C2=A0 i-cache-block-size =3D <64>; + =C2=A0 i-cache-sets =3D <64>; + =C2=A0 i-cache-size =3D <16384>; + =C2=A0 i-tlb-sets =3D <1>; + =C2=A0 i-tlb-size =3D <32>; + =C2=A0 mmu-type =3D "riscv,sv39"; + =C2=A0 reg =3D <0x1>; + + =C2=A0 cpu1_intc: interrupt-controller { +=C2=A0 =C2=A0 #interrupt-cells =3D <1>; +=C2=A0 =C2=A0 compatible =3D "riscv,cpu-intc"; +=C2=A0 =C2=A0 interrupt-controller; + =C2=A0 }; +=C2=A0 }; + }; + + clkc: misc_clk { +=C2=A0 compatible =3D "fixed-clock"; +=C2=A0 #clock-cells =3D <0>; +=C2=A0 clock-output-names =3D "clkc"; +=C2=A0 clock-frequency =3D <100000000>; + }; + + sdhci_clock: sdhci_clck { +=C2=A0 compatible =3D "fixed-clock"; +=C2=A0 #clock-cells =3D <0>; +=C2=A0 clock-output-names =3D "sdhci_clock"; +=C2=A0 clock-frequency =3D <25000000>; + }; + + i2c0_clock: i2c0_clck { +=C2=A0 compatible =3D "fixed-clock"; +=C2=A0 #clock-cells =3D <0>; +=C2=A0 clock-output-names =3D "i2c0_clock"; +=C2=A0 clock-frequency =3D <100000000>; + }; + + soc { +=C2=A0 #address-cells =3D <2>; +=C2=A0 #size-cells =3D <2>; +=C2=A0 compatible =3D "bosc,nanhu-v3a-soc", "simple-bus"; +=C2=A0 ranges; + +=C2=A0 clint0: clint@38000000 { + =C2=A0 compatible =3D "riscv,clint0"; + =C2=A0 interrupts-extended =3D <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &c= pu1_intc 7>; + =C2=A0 reg =3D <0x0 0x38000000 0x0 0x10000>; + =C2=A0 reg-names =3D "control"; + =C2=A0 clock-frequency-mhz =3D <10>; +=C2=A0 }; + +=C2=A0 plic: interrupt-controller@3c000000 { + =C2=A0 #interrupt-cells =3D <1>; + =C2=A0 compatible =3D "riscv,plic0"; + =C2=A0 interrupt-controller; + =C2=A0 interrupts-extended =3D <&cpu0_intc 0xb &cpu0_intc 0x9 &cpu1_intc = 0xb &cpu1_intc 0x9>; + =C2=A0 reg =3D <0 0x3c000000 0 0x4000000>; + =C2=A0 reg-names =3D "control"; + =C2=A0 riscv,max-priority =3D <7>; + =C2=A0 riscv,ndev =3D <128>; +=C2=A0 }; + +=C2=A0 ethernet0: ethernet@190000 { + =C2=A0 compatible =3D "st,stm32-dwmac", "snps,dwmac-3.50a"; + =C2=A0 reg =3D <0 0x190000 0 0x10000>; + =C2=A0 reg-names =3D "stmmaceth"; + =C2=A0 interrupt-parent =3D <&plic>; + =C2=A0 interrupts =3D <76 75 74>; + =C2=A0 interrupt-names =3D "eth_lpi", "macirq", "eth_wake_irq"; + =C2=A0 clock-names =3D "stmmaceth"; + =C2=A0 clocks =3D <&clkc>; + =C2=A0 snps,pbl =3D <2>; + =C2=A0 snps,mixed-burst; + =C2=A0 phy-mode =3D "rgmii"; + =C2=A0 phy-handle =3D <&phy0>; + =C2=A0 mdio0: mdio { +=C2=A0 =C2=A0 #address-cells =3D <0x1>; +=C2=A0 =C2=A0 #size-cells =3D <0x0>; +=C2=A0 =C2=A0 compatible =3D "snps,dwmac-mdio"; +=C2=A0 =C2=A0 phy0: phy@0 { + =C2=A0 =C2=A0 phyaddr =3D <0x0>; + =C2=A0 =C2=A0 compatible =3D "marvell,88E1510"; + =C2=A0 =C2=A0 device_type =3D "ethernet-phy"; + =C2=A0 =C2=A0 reg =3D <0x0>; +=C2=A0 =C2=A0 }; +=C2=A0 =C2=A0 phy1: phy@1 { + =C2=A0 =C2=A0 phyaddr =3D <0x1>; + =C2=A0 =C2=A0 compatible =3D "marvell,88E1510"; + =C2=A0 =C2=A0 device_type =3D "ethernet-phy"; + =C2=A0 =C2=A0 reg =3D <0x1>; +=C2=A0 =C2=A0 }; + =C2=A0 }; +=C2=A0 }; + +=C2=A0 ethernet1: ethernet@1a0000 { + =C2=A0 compatible =3D "st,stm32-dwmac", "snps,dwmac-3.50a"; + =C2=A0 reg =3D <0 0x1a0000 0 0x10000>; + =C2=A0 reg-names =3D "stmmaceth1"; + =C2=A0 interrupt-parent =3D <&plic>; + =C2=A0 interrupts =3D <73 72 71>; + =C2=A0 interrupt-names =3D "eth_lpi", "macirq", "eth_wake_irq"; + =C2=A0 clock-names =3D "stmmaceth"; + =C2=A0 clocks =3D <&clkc>; + =C2=A0 snps,pbl =3D <2>; + =C2=A0 snps,mixed-burst; + =C2=A0 phy-mode =3D "rgmii"; + =C2=A0 fixed-link{ +=C2=A0 =C2=A0 speed =3D=C2=A0 <1000>; +=C2=A0 =C2=A0 full-duplex; +=C2=A0 =C2=A0 pause; +=C2=A0 =C2=A0 asym-pause; + =C2=A0 }; +=C2=A0 }; + +=C2=A0 sdhci2: sdhci@1200000 { + =C2=A0 compatible =3D "snps,dwcmshc-sdhci"; + =C2=A0 reg =3D <0 0x1200000 0 0x20000>; + =C2=A0 interrupt-parent =3D <&plic>; + =C2=A0 interrupts =3D <77 78>; + =C2=A0 clocks =3D <&sdhci_clock>; + =C2=A0 clock-names =3D "core"; + =C2=A0 no-1-8-v; + =C2=A0 disable-wp; + =C2=A0 bus-width =3D <4>; + =C2=A0 max_req_size =3D <4096>; + =C2=A0 status =3D "okay"; +=C2=A0 }; + +=C2=A0 i2c@70000 { + =C2=A0 compatible =3D "snps,designware-i2c"; + =C2=A0 #address-cells =3D <1>; + =C2=A0 #size-cells =3D <0>; + =C2=A0 reg =3D <0x0 0x70000 0x0 0x10000>; + =C2=A0 interrupts =3D <66>; + =C2=A0 interrupt-parent =3D <&plic>; + =C2=A0 clock-frequency =3D <100000>; + =C2=A0 clocks =3D <&i2c0_clock>; + =C2=A0 status =3D "okay"; +=C2=A0 }; + +=C2=A0 i2c@80000 { + =C2=A0 compatible =3D "snps,designware-i2c"; + =C2=A0 #address-cells =3D <1>; + =C2=A0 #size-cells =3D <0>; + =C2=A0 reg =3D <0x0 0x80000 0x0 0x10000>; + =C2=A0 interrupts =3D <65>; + =C2=A0 interrupt-parent =3D <&plic>; + =C2=A0 clock-frequency =3D <100000>; + =C2=A0 clocks =3D <&i2c0_clock>; + =C2=A0 status =3D "okay"; +=C2=A0 }; + +=C2=A0 uart0: serial@50000 { + =C2=A0 compatible =3D "ns16550a"; + =C2=A0 reg =3D <0x0 0x50000 0x0 0x10000>; + =C2=A0 reg-shift =3D <0x02>; + =C2=A0 reg-io-width =3D <0x04>; + =C2=A0 interrupt-parent =3D <&plic>; + =C2=A0 interrupts =3D <68>; + =C2=A0 clock-frequency =3D <100000000>; + =C2=A0 status =3D "okay"; +=C2=A0 }; + }; + + memory: memory@100000000 { +=C2=A0 device_type =3D "memory"; +=C2=A0 reg =3D <0x0 0x80000000 0x2 0x00000000>; + }; + + aliases { +=C2=A0 serial0 =3D &uart0; + }; + + chosen { +=C2=A0 bootargs =3D "console=3DttyS0,115200 earlycon"; +=C2=A0 stdout-path =3D "serial0:115200n8"; + }; +}; -- 2.43.0