The following commit has been merged into the perf/core branch of tip:

Commit-ID:     7ae5f58517a6604ea86ae2b34cc7252d13d37180
Gitweb:        https://git.kernel.org/tip/7ae5f58517a6604ea86ae2b34cc7252d13d37180
Author:        Dapeng Mi <dapeng1.mi@linux.intel.com>
AuthorDate:    Fri, 15 May 2026 14:11:42 +08:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 19 May 2026 13:49:05 +02:00

perf/x86/intel: Update event constraints and cache_extra_regsfor SRF

Update perf hard-coded event constraints and cache_extra_regs[] for
Sierra Forest according to the latest SRF perfmon events (V1.17).

SRF has same uarch (crestmont) as MTL E-core and shares same perf
events, so directly apply the crestmont perf events.

SRF perfmon events:
https://github.com/intel/perfmon/blob/main/SRF/events/sierraforest_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-11-dapeng1.mi@linux.intel.com
---
 arch/x86/events/intel/core.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 332761d..c4efb87 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -8136,8 +8136,7 @@ __init int intel_pmu_init(void)
 
 	case INTEL_ATOM_CRESTMONT:
 	case INTEL_ATOM_CRESTMONT_X:
-		intel_pmu_init_grt(NULL);
-		x86_pmu.extra_regs = intel_cmt_extra_regs;
+		intel_pmu_init_cmt(NULL);
 		intel_pmu_pebs_data_source_cmt();
 		x86_pmu.pebs_latency_data = cmt_latency_data;
 		x86_pmu.get_event_constraints = cmt_get_event_constraints;