From nobody Mon May 25 00:09:52 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89D9B34D4EA; Wed, 20 May 2026 08:33:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266025; cv=none; b=F0kO22c9iqvxdLgYoi/Qu8DZj7LVuYADQjhSBTpRfbEC/lKXqT6klEj+12wi8/2WZiqzOOXz3abRis0VRvNJFlVh1nh1q/QSnaVhJA3c+apgIIbs4wq5OuefGCsZxxdfSc4UylX5wxiz/mKNTDz9NpIVkveRUZT+/VIaGFsQgCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266025; c=relaxed/simple; bh=Guo37qd1GjdXFCZAtXiDl/10JLsQ8KSQvhBASPF/H3E=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=o8bCGxcLPI1AQlk97HzbFdwMz0bijgWThWc28DKilYgVU9+236O/o4i7wtJHS6iklATgq4CRQM7Q2GhuUpQwJUWTuYEwJzxdoZRzSOnVNoPaYsoeVqF2GrOCwjZ68A6nrDd7W3BvCSUkmwpzZ+QwdY77d/OVJtVd0E3hmJex7wY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=IXq0MCHc; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zr8xnE+j; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="IXq0MCHc"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zr8xnE+j" Date: Wed, 20 May 2026 08:33:41 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266023; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x3ia5fdQu+QC3sjc5IXXVpaQ9AQOVDc6OxCaHu/Yj2M=; b=IXq0MCHcZMEKXrHTZUcgUshGumHTQ9chhpdVCxzZv3eSJqu+lIVmzqdn/GPn8c9KfeswXQ 7Lg1X5nC/2wY7mRNSnBZrxUKa/DeOl3ZSbrSL9eoL3ODa5ES561QepXQ9hL8O9Px0x22jU p/0XlCOvAc2zT0ls81Tm8So8cNw8lq7zYWssHL+m1SEHBYKv5ccAOIcZeA7a0VCnIcDoCd bQJPtacf9rJ+QCfg7mjjOY9lIO3Ulz54J3cUStl0SmjRK6E5KveduhUhYNd9WbeV6gl1ux kiYYK/80YPl3ImAGLE7NehrZIdG37kTGohecs/R5iBA0Oy0kWo4aMdYaxS7igg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266023; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x3ia5fdQu+QC3sjc5IXXVpaQ9AQOVDc6OxCaHu/Yj2M=; b=zr8xnE+jNR4AcDEjTQiYTPpVkI7hl+3VrOqLrj4OEVbkujd53Sy1pJvKDaD80d7g3rizqM 62aCx1YsOCwxG3DA== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Update event constraints and cache_extra_regsfor SRF Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515061143.338553-11-dapeng1.mi@linux.intel.com> References: <20260515061143.338553-11-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926602140.711.12293765857087654036.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 7ae5f58517a6604ea86ae2b34cc7252d13d37180 Gitweb: https://git.kernel.org/tip/7ae5f58517a6604ea86ae2b34cc7252d1= 3d37180 Author: Dapeng Mi AuthorDate: Fri, 15 May 2026 14:11:42 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 19 May 2026 13:49:05 +02:00 perf/x86/intel: Update event constraints and cache_extra_regsfor SRF Update perf hard-coded event constraints and cache_extra_regs[] for Sierra Forest according to the latest SRF perfmon events (V1.17). SRF has same uarch (crestmont) as MTL E-core and shares same perf events, so directly apply the crestmont perf events. SRF perfmon events: https://github.com/intel/perfmon/blob/main/SRF/events/sierraforest_core.json Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-11-dapeng1.mi@linux.in= tel.com --- arch/x86/events/intel/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 332761d..c4efb87 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -8136,8 +8136,7 @@ __init int intel_pmu_init(void) =20 case INTEL_ATOM_CRESTMONT: case INTEL_ATOM_CRESTMONT_X: - intel_pmu_init_grt(NULL); - x86_pmu.extra_regs =3D intel_cmt_extra_regs; + intel_pmu_init_cmt(NULL); intel_pmu_pebs_data_source_cmt(); x86_pmu.pebs_latency_data =3D cmt_latency_data; x86_pmu.get_event_constraints =3D cmt_get_event_constraints;