On 24/6/23 19:41, Philippe Mathieu-Daudé wrote:
> This series is part of the single binary effort.
>
> All accelerator will share their per-vCPU context in
> an opaque 'accel' pointer within the CPUState.
>
> First handle HAX/NVMM/WHPX/HVF. KVM and TCG will follow
> as two different (bigger) follow-up series.
>
> Except HVF/intel, all has been (cross-)build tested.
>
> I plan to send the PR myself.
>
> Since v2:
> - Addressed rth's review comments
> - Added rth's R-b tag
>
> Since v1:
> - Addressed rth's review comments
> - Added rth's R-b tag
> - Converted HVF intel (untested)
> - Rebased
>
> Philippe Mathieu-Daudé (16):
> MAINTAINERS: Update Roman Bolshakov email address
> accel: Document generic accelerator headers
> accel: Remove unused hThread variable on TCG/WHPX
> accel: Fix a leak on Windows HAX
> accel: Destroy HAX vCPU threads once done
> accel: Rename 'hax_vcpu' as 'accel' in CPUState
> accel: Rename HAX 'struct hax_vcpu_state' -> AccelCPUState
> accel: Move HAX hThread to accelerator context
> accel: Remove NVMM unreachable error path
> accel: Rename NVMM 'struct qemu_vcpu' -> AccelCPUState
> accel: Inline NVMM get_qemu_vcpu()
> accel: Remove WHPX unreachable error path
> accel: Rename WHPX 'struct whpx_vcpu' -> AccelCPUState
> accel: Inline WHPX get_whpx_vcpu()
> accel: Rename 'cpu_state' -> 'cs'
> accel: Rename HVF 'struct hvf_vcpu_state' -> AccelCPUState
Except the MAINTAINERS patch, all the rest is reviewed, so I plan
to send a PR tomorrow (dropping the first patch, nobody complained
about Roman email bouncing for months so we can keep ignoring the
automated emails).